Advertise the same chipid as A740 to userspace for now, until
the whole chipid/revn gets sorted out.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Konrad Dybcio authored 1 year ago and Abel Vesa committed 1 year ago

New GPUs still use the lower 2 bytes of the chip id (in whatever form
it comes) to signify silicon revision. Drop the warning that makes it
sound as if that was unintended.

Fixes: 90b593ce ("drm/msm/adreno: Switch to chip-id for identifying GPU")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

A705 builds upon the A740 IP, but is considered to be a different IP
So add support for it separately even if it looks similar to A740.
Do this because of the chip ID difference.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Enable the CPUCP mailbox controller driver as built-in.
Needed by the new Qualcomm X1E80100 platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Enable as modules the CAM, GPU, DISP and TCSR clock controllers for
Qualcomm X1E80100 platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Sibi Sankar authored 1 year ago and Abel Vesa committed 1 year ago

The UEFI loads a lite variant of the ADSP firmware to support charging
use cases. The kernel needs to unload and reload it with the firmware
that has full feature support for audio. This patch arbitarily shutsdown
the lite firmware before loading the full firmware.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>

Abhinav Kumar authored 1 year ago and Abel Vesa committed 1 year ago

It's certainly possible that for large resolutions a single DPU SSPP
cannot process the image without exceeding the MDP clock limits but
it can still process it in multirect mode because the source rectangles
will get divided and can fall within the MDP clock limits.

If the SSPP cannot process the image even in multirect mode, then it
will be rejected in dpu_plane_atomic_check_pipe().

Hence try using multirect for resolutions which cannot be processed
by a single SSPP without exceeding the MDP clock limits.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>

Add definitions for the display hardware used on the Qualcomm X1E80100
platform.

Co-developed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

The Qualcomm X1E80100 platform has a single DisplayPort controller, with
the same design as SM8550, so add support for this by reusing the SM8550
definition.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Abhinav Kumar authored 1 year ago and Abel Vesa committed 1 year ago

On platforms where the endpoint used is on port@0, looking for port@1
instead results in just ignoring the max link-frequencies altogether.
Look at port@0 first, then, if not found, look for port@1.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>

Add support for MDSS on X1E80100.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add support for the SDC ATNA45AF01 panel.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add the X1E80100 DPU compatible to clients compatible list, as it also
needs the workarounds.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Sibi Sankar authored 1 year ago and Abel Vesa committed 1 year ago

Add support for CPUSS Control Processor (CPUCP) mailbox controller,
this driver enables communication between AP and CPUCP by acting as
a doorbell between them.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Sibi Sankar authored 1 year ago and Abel Vesa committed 1 year ago

Add support for PIL loading on ADSP and CDSP on X1E80100 SoCs.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add both UCSI and Battery Management support for X1E80100.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add the compatible and the driver data for X1E80100.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

The X1E80100 platform has two instances of the USB3 UNI phy attached
to the multi-port USB controller, add definition for these.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add the X1E80100 G3 configurations.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add the X1E80100 G4 configurations.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

The X1E80100 has three copies of an USB/DP compbo PHY, add support for this
to the Qualcomm QMP PHY driver.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

The SMB2360 PMICs contain the same eUSB2 repeater as the PM8550B,
so add dedicated compatible for SMB82360.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add the X1E80100 to the list of supported PHYs for eUSB2
SNPS driver.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

The Qualcomm X1E80100 platform has a number of eDP and DP PHY instances,
add support for these.

Co-developed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

A new SoC bumps up the HW version of QMP phy to v7 for USB and PCIE.
Add the new qserdes TX RX offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

There is a variant of V6 offsets that are different and it is found
QMP PHY N4.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

A new SoC bumps up the HW version of QMP phy to v7 for USB
and PCIE g3x2. Add the new qserdes com offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

A new SoC bumps up the HW version of QMP phy to v7 for USB.
Add the new PCS USB specific offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

A new SoC bumps up the HW version of QMP phy to v7 for USB,
and PCIE. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

These new ones will be used by upcomming Qualcomm platforms.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add some missing V6 registers offsets that will be used later on
by other platforms.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add the X1E80100 compatible to the list of supported PHYs.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Add a dt-bindings compatible string for the Qualcomm's SMB2360 PMIC.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Rajendra Nayak authored 1 year ago and Abel Vesa committed 1 year ago

Add the camcc clock driver for x1e80100

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Rajendra Nayak authored 1 year ago and Abel Vesa committed 1 year ago

Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add
support for it.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>

The TCSR clock controller found on X1E80100 provides refclks
for PCIE, USB and UFS. Add clock driver for it.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Rajendra Nayak authored 1 year ago and Abel Vesa committed 1 year ago

Add Graphics Clock Controller (GPUCC) support for X1E80100 platform.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Rajendra Nayak authored 1 year ago and Abel Vesa committed 1 year ago

Add the dispcc clock driver for x1e80100.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Rajendra Nayak authored 1 year ago and Abel Vesa committed 1 year ago

Add bindings documentation for the X1E80100 Camera Clock Controller.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Rajendra Nayak authored 1 year ago and Abel Vesa committed 1 year ago

Add bindings documentation for the X1E80100 Graphics Clock Controller.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>