Tags

[RFT] fastboot: add support for generic block flashing

This serie permits using any block device as target
for fastboot by moving the generic block logic into
a common set of helpers and also use them as generic
backend.

The erase logic has been extended to support software
erase since only 2 block drivers exposes the erase
operation.

Tests are welcome to make sure this series doesn't
introduce any regressions on the emmc backend.

To: Tom Rini <trini@konsulko.com>
To: Mattijs Korpershoek <mkorpershoek@baylibre.com>
To: Mattijs Korpershoek <mkorpershoek@kernel.org>
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v3:
- Move Kconfig/Makefile changes over the 2 patches
- Relicence to GPL2 with Dmitrii approval
- Move soft erase in a separate function
- Update help text of Kconfig BLOCK entries
- Add warning at init if MMC was selected with BLOCK backend
- Link to v2: https://lore.kernel.org/r/20250409-topic-fastboot-blk-v2-0-c676f21d414f@linaro.org

Changes in v2:
- Dropped applied virtio erase patch
- Reorganize patches, introducing helpers first, using them in mmc afterwards
- Added soft-erase logic
- Added move helpers to handle the partitions erase & flash from emmc
- Fixed const var on last patch
- Link to v1: https://lore.kernel.org/all/20240306185921.1854109-1-dimorinny@google.com/

---
Dmitrii Merkurev (3):
      fastboot: blk: introduce fastboot block flashing support
      fastboot: blk: switch emmc to use the block helpers
      fastboot: integrate block flashing back-end

 drivers/fastboot/Kconfig      |  28 +++-
 drivers/fastboot/Makefile     |   4 +-
 drivers/fastboot/fb_block.c   | 323 ++++++++++++++++++++++++++++++++++++++++++
 drivers/fastboot/fb_command.c |   8 ++
 drivers/fastboot/fb_common.c  |  22 ++-
 drivers/fastboot/fb_getvar.c  |   8 +-
 drivers/fastboot/fb_mmc.c     | 210 ++-------------------------
 include/fb_block.h            | 105 ++++++++++++++
 8 files changed, 502 insertions(+), 206 deletions(-)
---
base-commit: 4d3b5c679bc9d5c6cbbeedcc1e4a186f1cc35541
change-id: 20250408-topic-fastboot-blk-c5e14cd59224

Best regards,

[RFT] fastboot: add support for generic block flashing

This serie permits using any block device as target
for fastboot by moving the generic block logic into
a common set of helpers and also use them as generic
backend.

The erase logic has been extended to support software
erase since only 2 block drivers exposes the erase
operation.

Tests are welcome to make sure this series doesn't
introduce any regressions on the emmc backend.

To: Tom Rini <trini@konsulko.com>
To: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v2:
- Dropped applied virtio erase patch
- Reorganize patches, introducing helpers first, using them in mmc afterwards
- Added soft-erase logic
- Added move helpers to handle the partitions erase & flash from emmc
- Fixed const var on last patch
- Link to v1: https://lore.kernel.org/all/20240306185921.1854109-1-dimorinny@google.com/

---
Dmitrii Merkurev (3):
      fastboot: blk: introduce fastboot block flashing support
      fastboot: blk: switch emmc to use the block helpers
      fastboot: integrate block flashing back-end

 drivers/fastboot/Kconfig      |  20 ++-
 drivers/fastboot/Makefile     |   4 +-
 drivers/fastboot/fb_block.c   | 313 ++++++++++++++++++++++++++++++++++++++++++
 drivers/fastboot/fb_command.c |   8 ++
 drivers/fastboot/fb_common.c  |  16 ++-
 drivers/fastboot/fb_getvar.c  |   8 +-
 drivers/fastboot/fb_mmc.c     | 210 ++--------------------------
 include/fb_block.h            | 104 ++++++++++++++
 8 files changed, 477 insertions(+), 206 deletions(-)
---
base-commit: f892a7f397a66d8d09f418d1e0e06dfb48bac27d
change-id: 20250408-topic-fastboot-blk-c5e14cd59224

Best regards,

part_efi: cache last scanned GPT for next partition

The actual architecture of the EFI part parser means the
entire GPT partition table needs to be parsed for each
part_info() callback.

Since the default part scan code will always scan up to
128 partitions for a block, and devices with an UFS chip
with up to 8 LUNs are very common in the field, this means
a complete GPT parsing and validation will be done
up to 1024 times instead of 8 on such devices.

The GPT parsing can be cached between each part_info()
call speed up to 3x on the worse condition when the CPU
i-cache and d-cache are disabled, like in the SPL.

The new part API implementation does caching each time
a correct GPT has been parsed and verified and will match
the blk_desc and LBA to serve the cached data or force
a re-parsing.

In order to allow GPT manipulation, the new API is only
called when scanning the partitions for a disk, all the
calls will be called uncached.

On the SM8650 QRD platform with a KIOXIA THGJFJT1E45BATPC
configured with 8 LUNs, the scsi scan takes 0.2s with both
CPU caches enabled, but when disabling both CPU caches it
goes up to 4s to do the full scan of all 8 LUN partitions.

With this change the scan takes only 0.18s with both CPU
caches enabled running 1.1x times faster, and with both CPU
caches disabled the full scan takes only 1.27s running
3x faster.

While 20ms could look negligeable, it's still a 20ms gain
in the boot flow and a non negligeable reduction in
calculation and memory allocation since for each scan
it would allocate and free the gpt_pte table up to
1024 times, now it would only do 8 allocations, reducing
memory fragmentation.

To: Tom Rini <trini@konsulko.com>
To: Ilias Apalodimas <ilias.apalodimas@linaro.org>
To: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Changes in v2:
- add part_info_get_cached API
- only use cache when called from part_info_get_cached
- Link to v1: https://lore.kernel.org/all/20250327-u-boot-efi-part-cache-v1-1-be6b69c0698b@linaro.org

---
Neil Armstrong (3):
      part: add part_get_info_cached() API
      part: efi: add GPT PTE cache used with part_get_info_cached() API
      block: use part_get_info_cached() API when scanning partitions

 disk/part.c                |  55 +++++++++++++++++-----
 disk/part_efi.c            | 114 ++++++++++++++++++++++++++++++++++++++-------
 drivers/block/blk-uclass.c |   7 ++-
 include/part.h             |  44 +++++++++++++++++
 4 files changed, 189 insertions(+), 31 deletions(-)
---
base-commit: 5ca70325b64f760bf4190f206a0e88dda495e3d2
change-id: 20250408-topic-gpt-cache-11f770f42f1e

Best regards,

[RFC/RFT] gpio: qcom: rewritte SPMI gpio driver from Linux driver

The current SPMI gpio driver is very old and doesn't support
pin state tracking to fully support the whole pinconf calls.

The simplest is to rewritte the driver using the v6.14 Linux
driver and fully implement pinctrl, pinmux, pinconf and gpio
support using all the newer interfaces.

The goal is to deprecate the old one it has been validated
on currently supported hardware.

To: Tom Rini <trini@konsulko.com>
To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@kernel.org>
Cc: u-boot@lists.denx.de
Cc: u-boot-qcom@groups.io
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (2):
      gpio: qcom: add new driver for SPMI gpios
      gpio: qcom: move pm8550 gpio to new driver

 drivers/gpio/Makefile         |    2 +-
 drivers/gpio/qcom_pmic_gpio.c |   20 +-
 drivers/gpio/qcom_spmi_gpio.c | 1035 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1037 insertions(+), 20 deletions(-)
---
base-commit: 5ca70325b64f760bf4190f206a0e88dda495e3d2
change-id: 20250401-topic-sm8x50-pmic-gpio-pinctrl-new-2588c35a461c

Best regards,

spmi: msm: fix pid mapping for v5 & v7 controllers

The v5 & v7 controllers has complex mapping for
different Execution Environment, and v7 supports
two busses within the same controller so it needs
some special care when parsing the hardware map
table to get the proper read & write channels.

Test are welcome, especially for v5 controllers.

Tested on HDK8550, QRD8550 & QRD8650.

To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@kernel.org>
To: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
To: Tom Rini <trini@konsulko.com>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (4):
      spmi: msm: use real number of channels for v5 & v7
      spmi: msm: factor out channel mapping for v5 & v7
      spmi: msm: introduce SPMI_CHANNEL_VALID flag
      spmi: msm: correctly handle multiple mapping entries

 drivers/spmi/spmi-msm.c | 59 ++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 49 insertions(+), 10 deletions(-)
---
base-commit: 4adbf64ff8d8c730223fd8ae299d770bebb6fe86
change-id: 20250328-topic-sm8x50-spmi-fix-1e2b433a6ffd

Best regards,

(no cover subject)

To: Tom Rini <trini@konsulko.com>
Cc: caleb.connolly@linaro.org
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (1):
      pci: dw_common: Set INCREASE_REGION_SIZE flag based on limit address

 drivers/pci/pcie_dw_common.c | 8 ++++++--
 drivers/pci/pcie_dw_common.h | 2 ++
 2 files changed, 8 insertions(+), 2 deletions(-)
---
base-commit: b3c09eb36529fbb277bec17b35e638f42cb33683
change-id: 20250206-topic-sm8x50-pcie-dw-atu-increase-region-size-878465356c54

Best regards,

ufs: core: initial cleanup and defines sync with Linux v6.12

This serie fixes the build and checkpatch warnings, and
does a split of the ufs.h into a separate ufshci.h which
helps syndhronizing the defines from Linux v6.12.

No functional changes intended, tests on hardware
are welcome.

To: Bhupesh Sharma <bhupesh.linux@gmail.com>
To: Neha Malcom Francis <n-francis@ti.com>
To: Tom Rini <trini@konsulko.com>
Cc: michal.simek@amd.com
CC: marek.vasut+renesas@mailbox.org
Cc: bmeng.cn@gmail.com
Cc: venkatesh.abbarapu@amd.com
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Changes in v2:
- Colect tested & review tags
- drop EXPORT SYMBOL of ufshcd_map_desc_id_to_length in patch 2
- Link to v1: https://lore.kernel.org/r/20241120-topic-ufs-cleanup-v1-0-a5cef54b1cdc@linaro.org

---
Neil Armstrong (6):
      ufs: core: include missing include/ufs.h
      ufs: core: mark unexported functions as static
      ufs: core: cosmetic fixups
      ufs: core: move ufshci defines in a separate header
      ufs: core: sync unipro.h with Linux v6.12
      ufs: core: sync ufshci.h with Linux v6.12

 drivers/ufs/ufs.c    |  44 +++--
 drivers/ufs/ufs.h    | 335 +-----------------------------------
 drivers/ufs/ufshci.h | 469 +++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/ufs/unipro.h | 128 ++++++++------
 4 files changed, 571 insertions(+), 405 deletions(-)
---
base-commit: d580a013cca67a8115fb88d260498bde181709a1
change-id: 20241120-topic-ufs-cleanup-23671e3fc9e9

Best regards,

rng: msm: support newer SoCs

Add support for RNG on newer SoCs which shares the
RNG hardware between different Execution Environments (EE).

Also enable it by default to fill KASL seed when running Linux.

To: Robert Marko <robert.marko@sartura.hr>
To: Luka Perkov <luka.perkov@sartura.hr>
To: Sughosh Ganu <sughosh.ganu@linaro.org>
To: Heinrich Schuchardt <xypron.glpk@gmx.de>
To: Tom Rini <trini@konsulko.com>
To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@linaro.org>
Cc: u-boot@lists.denx.de
Cc: u-boot-qcom@groups.io
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (2):
      rng: msm: add support for newer Qualcomm hwrandom IPs
      configs: qcom_defconfig: enable RNG driver and command

 configs/qcom_defconfig |  3 +++
 drivers/rng/msm_rng.c  | 13 ++++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)
---
base-commit: dc1859f8d2ac3faaa5e2e1d465ec4bd8980520a5
change-id: 20241125-topic-sm8x50-rng-714cd0012391

Best regards,

pci: Add support for Qualcomm PCIe controller

Add support for the DWC PCIe controllers found
on the Qualcomm SoCs, it requires introducing
pcie_dw_find_capability() to properly configure
the Host controller capabilities.

To: Tom Rini <trini@konsulko.com>
To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@linaro.org>
Cc: u-boot@lists.denx.de
Cc: u-boot-qcom@groups.io
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (2):
      pci: pcie_dw_common: introduce pcie_dw_find_capability()
      pci: Add support for Qualcomm PCIe controller

 drivers/pci/Kconfig          |   8 +
 drivers/pci/Makefile         |   1 +
 drivers/pci/pcie_dw_common.c |  42 ++++
 drivers/pci/pcie_dw_common.h |   2 +
 drivers/pci/pcie_dw_qcom.c   | 571 +++++++++++++++++++++++++++++++++++++++++++
 include/pci.h                |   4 +
 6 files changed, 628 insertions(+)
---
base-commit: 7fe55182d9263a62e18b450c97bdf0b8031e5667
change-id: 20241125-topic-pcie-controller-cf11210bf5b3

Best regards,

(no cover subject)

To: Tom Rini <trini@konsulko.com>
To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@linaro.org>
Cc: u-boot@lists.denx.de
Cc: u-boot-qcom@groups.io
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (1):
      phy: qcom: add QMP PCIe PHY driver

 drivers/phy/qcom/Kconfig                           |    6 +
 drivers/phy/qcom/Makefile                          |    1 +
 drivers/phy/qcom/phy-qcom-qmp-pcie-qhp.h           |  123 +++
 drivers/phy/qcom/phy-qcom-qmp-pcie.c               | 1131 ++++++++++++++++++++
 drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v3.h        |   17 +
 drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4.h        |   72 ++
 drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4_20.h     |   19 +
 drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5.h        |   17 +
 drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5_20.h     |   23 +
 drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6.h        |   17 +
 drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6_20.h     |   25 +
 drivers/phy/qcom/phy-qcom-qmp-pcs-v5.h             |   34 +
 drivers/phy/qcom/phy-qcom-qmp-pcs-v6.h             |   32 +
 drivers/phy/qcom/phy-qcom-qmp-pcs-v6_20.h          |   19 +
 drivers/phy/qcom/phy-qcom-qmp-qserdes-ln-shrd-v6.h |   32 +
 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6.h    |   83 ++
 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6_20.h |   51 +
 17 files changed, 1702 insertions(+)
---
base-commit: 7fe55182d9263a62e18b450c97bdf0b8031e5667
change-id: 20241125-topic-pcie-phy-542f745f39b5

Best regards,

clk: qcom: add PCIe clocks

Add the PCIe clocks for the SM8550, SM8650 and X1E80100
platforms to enable support for PCIe feature.

Depends on:
- https://lore.kernel.org/all/20241118-topic-x1e80100-clk-v1-0-8841e87ad81f@linaro.org/

To: Lukasz Majewski <lukma@denx.de>
To: Sean Anderson <seanga2@gmail.com>
To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@linaro.org>
To: Tom Rini <trini@konsulko.com>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (4):
      clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock
      clk: qcom: sm8550: add support for PCIe clocks
      clk: qcom: sm8650: add support for PCIe clocks
      clk: qcom: x1e80100: add support for PCIe clocks

 drivers/clk/qcom/clock-qcom.c     | 19 ++++++++++++++
 drivers/clk/qcom/clock-qcom.h     |  2 ++
 drivers/clk/qcom/clock-sm8550.c   | 36 ++++++++++++++++++++++++++
 drivers/clk/qcom/clock-sm8650.c   | 36 ++++++++++++++++++++++++++
 drivers/clk/qcom/clock-x1e80100.c | 54 +++++++++++++++++++++++++++++++++++++++
 5 files changed, 147 insertions(+)
---
base-commit: c7934881aa75d34aea2493322de0a417524ebf4a
change-id: 20241125-topic-pcie-clk-8e345d8ace7a

Best regards,

pinctrl: qcom: add clk_req functions

Add the missing PCIe clk_req functions for the SM8550, SM8650
and X1E80100 TLMM.

Depends on:
- https://lore.kernel.org/all/20241115-topic-x1e80100-pinctrl-v1-0-35f984226e47@linaro.org/

To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@linaro.org>
To: Tom Rini <trini@konsulko.com>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (3):
      pinctrl: qcom: sm8550: add pcie1_clk_req_n function
      pinctrl: qcom: sm8650: add pcie[01]_clk_req_n function
      pinctrl: qcom: x1e80100: add pcie[3456ab]_clk functions

 drivers/pinctrl/qcom/pinctrl-sm8550.c   | 1 +
 drivers/pinctrl/qcom/pinctrl-sm8650.c   | 2 ++
 drivers/pinctrl/qcom/pinctrl-x1e80100.c | 5 +++++
 3 files changed, 8 insertions(+)
---
base-commit: 7a36c84ff57177ccd3107f62c8d14fa0093e0e76
change-id: 20241125-topic-pcie-pinctrl-77f1c184e73f

Best regards,

(no cover subject)

To: Jaehoon Chung <jh80.chung@samsung.com>
To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@linaro.org>
To: Tom Rini <trini@konsulko.com>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (1):
      regulator: qcom-rpmh-regulator: add support for pmc8380 regulators

 drivers/power/regulator/qcom-rpmh-regulator.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
---
base-commit: 7fe55182d9263a62e18b450c97bdf0b8031e5667
change-id: 20241125-topic-hamoa-pmc8380-rpmh-regulators-2b9460fcd7bd

Best regards,

image: android: misc fixes when using on Qualcomm platforms

When trying to use the Android boot image with header version 2
on recent Qualcomm platforms, we get into some troubles.

First the kernel in-place address can be > 32bit, then since
we use the Android mkbootimg, it uses the default load address
which isn't big enough to uncompress the kernel.

Finally, the ramdisk also uses a default load address, and
it should be taken in account like for the kernel address.

To: Tom Rini <trini@konsulko.com>
Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: Guillaume La Roque <glaroque@baylibre.com>
Cc: Caleb Connolly <caleb.connolly@linaro.org>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Changes in v2:
- Fix patch 2 prefix
- Fix patch 3 commit msg
- Fix patch 3 behavior when using boot image header version > 2, use the original ramdisk_ptr
- Link to v1: https://lore.kernel.org/r/20241016-topic-fastboot-fixes-mkbootimg-v1-0-94fd9340722b@linaro.org

---
Neil Armstrong (3):
      image: android: use ulong for kernel address
      image: android: do not boot XIP when kernel is compressed
      image: android: handle ramdisk default address

 boot/image-android.c    | 62 +++++++++++++++++++++++++++++++++++++------------
 include/android_image.h |  2 +-
 2 files changed, 48 insertions(+), 16 deletions(-)
---
base-commit: d5cab0d6adc26ec1bbd45c2fed101184d04454ae
change-id: 20241016-topic-fastboot-fixes-mkbootimg-8d73ab93db3d

Best regards,

(no cover subject)

To: Caleb Connolly <caleb.connolly@linaro.org>
To: Sumit Garg <sumit.garg@linaro.org>
To: Tom Rini <trini@konsulko.com>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (1):
      qcom_defconfig: enable PINCONF

 configs/qcom_defconfig | 1 +
 1 file changed, 1 insertion(+)
---
base-commit: d5cab0d6adc26ec1bbd45c2fed101184d04454ae
change-id: 20241017-topic-sm8x50-enable-pinconf-58ae8e77cd36

Best regards,

image: android: misc fixes when using on Qualcomm platforms

When trying to use the Android boot image with header version 2
on recent Qualcomm platforms, we get into some troubles.

First the kernel in-place address can be > 32bit, then since
we use the Android mkbootimg, it uses the default load address
which isn't big enough to uncompress the kernel.

Finally, the ramdisk also uses a default load address, and
it should be taken in account like for the kernel address.

To: Tom Rini <trini@konsulko.com>
Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: Guillaume La Roque <glaroque@baylibre.com>
Cc: Caleb Connolly <caleb.connolly@linaro.org>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Neil Armstrong (3):
      image: android: use ulong for kernel address
      boot: image-android: do not boot XIP when kernel is compressed
      image: android: handle ramdisk default address

 boot/image-android.c    | 60 +++++++++++++++++++++++++++++++++++++------------
 include/android_image.h |  2 +-
 2 files changed, 47 insertions(+), 15 deletions(-)
---
base-commit: d5cab0d6adc26ec1bbd45c2fed101184d04454ae
change-id: 20241016-topic-fastboot-fixes-mkbootimg-8d73ab93db3d

Best regards,

dwc3: gadget: properly fix cache operations

We experience huge problems with cache handling on Qualcomm
systems, and it appears the dcache handling in the DWC3 gadget
code is quite wrong and causes operational issues.

This serie fixes the dcache operations on unaligned data,
and properly invalidate buffers when reading back data from
hardware.

To: Marek Vasut <marex@denx.de>
To: Tom Rini <trini@konsulko.com>
To: Lukasz Majewski <lukma@denx.de>
To: Mattijs Korpershoek <mkorpershoek@baylibre.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Caleb Connolly <caleb.connolly@linaro.org>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Changes in v4:
- Go back to CACHELINE_SIZE, and do not use DMA_MINALIGN since it's not valid for all platforms
- Link to v3: https://lore.kernel.org/r/20241002-u-boot-dwc3-gadget-dcache-fixup-v3-0-5398088ef93c@linaro.org

Changes in v3:
- Cast addresses to (unsigned long) when calling invalidate_dcache_range()
- Drop unused CACHELINE_SIZE
- Fix warning by casting ctrl to uintptr_r when calling dwc3_invalidate_cache()
- Link to v2: https://lore.kernel.org/r/20240724-u-boot-dwc3-gadget-dcache-fixup-v2-0-65836d699a71@linaro.org

Changes in v2:
- Fix typo in drivers/usb/dwc3/core.h and rewrite patch 1 commit message
- Link to v1: https://lore.kernel.org/r/20240719-u-boot-dwc3-gadget-dcache-fixup-v1-0-58a5f026ea8e@linaro.org

---
Neil Armstrong (3):
      usb: dwc3: allocate setup_buf with dma_alloc_coherent()
      usb: dwc3: fix dcache flush range calculation
      usb: dwc3: invalidate dcache on buffer used in interrupt handling

 drivers/usb/dwc3/core.h   |  2 ++
 drivers/usb/dwc3/ep0.c    |  6 ++++--
 drivers/usb/dwc3/gadget.c | 10 ++++++----
 drivers/usb/dwc3/io.h     | 13 ++++++++++++-
 4 files changed, 24 insertions(+), 7 deletions(-)
---
base-commit: ddbcafeb53e7093c58488596bfce6d8823777c3a
change-id: 20240719-u-boot-dwc3-gadget-dcache-fixup-ea1e92758663

Best regards,

dwc3: gadget: properly fix cache operations

We experience huge problems with cache handling on Qualcomm
systems, and it appears the dcache handling in the DWC3 gadget
code is quite wrong and causes operational issues.

This serie fixes the dcache operations on unaligned data,
and properly invalidate buffers when reading back data from
hardware.

To: Marek Vasut <marex@denx.de>
To: Tom Rini <trini@konsulko.com>
To: Lukasz Majewski <lukma@denx.de>
To: Mattijs Korpershoek <mkorpershoek@baylibre.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Caleb Connolly <caleb.connolly@linaro.org>
Cc: u-boot-qcom@groups.io
Cc: u-boot@lists.denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Changes in v3:
- Cast addresses to (unsigned long) when calling invalidate_dcache_range()
- Drop unused CACHELINE_SIZE
- Fix warning by casting ctrl to uintptr_r when calling dwc3_invalidate_cache()
- Link to v2: https://lore.kernel.org/r/20240724-u-boot-dwc3-gadget-dcache-fixup-v2-0-65836d699a71@linaro.org

Changes in v2:
- Fix typo in drivers/usb/dwc3/core.h and rewrite patch 1 commit message
- Link to v1: https://lore.kernel.org/r/20240719-u-boot-dwc3-gadget-dcache-fixup-v1-0-58a5f026ea8e@linaro.org

---
Neil Armstrong (3):
      usb: dwc3: allocate setup_buf with dma_alloc_coherent()
      usb: dwc3: fix dcache flush range calculation
      usb: dwc3: invalidate dcache on buffer used in interrupt handling

 drivers/usb/dwc3/core.h   |  2 ++
 drivers/usb/dwc3/ep0.c    |  6 ++++--
 drivers/usb/dwc3/gadget.c | 10 ++++++----
 drivers/usb/dwc3/io.h     | 14 ++++++++++++--
 4 files changed, 24 insertions(+), 8 deletions(-)
---
base-commit: ddbcafeb53e7093c58488596bfce6d8823777c3a
change-id: 20240719-u-boot-dwc3-gadget-dcache-fixup-ea1e92758663

Best regards,

ufs: enhancements to support Qualcomm UFS controllers

This serie regroups all the fixes and base enhancements required to
support the Qualcomm UFS controllers in U-Boot.

This syncs headers & defines from Linux, and includes 2 set of
fixes that were sent separately:
- ufs: core: remove link_startup_again logic
- ufs: properly fix cache operations

Without those 2 sets, UFS cannot initialize on Qualcomm controlers
since v5, and a numerous of Cache issues makes any UFS controller
fail to initialize.

Since UFS core hasn't changed for a while, and since UFS is core
technology for the Qualcomm SoCs, I volunteer maintaininig the
UFS subsystem if Bhupesh & Neha Malcom Francis are ok with that.

It has been reported to show regressions on:
- TI K3 platforms (j721s2, j721e, j7200, j784s4) [1]
- AMD platform (amd_versal2_virt_defconfig) [2]

[1] https://lore.kernel.org/all/38f599a8-7094-4a04-8ff6-96fc8b9d168a@ti.com/
[2] https://lore.kernel.org/all/SA1PR12MB869713CA620F99077B75EF0E98632@SA1PR12MB8697.namprd12.prod.outlook.com/

To: Tom Rini <trini@konsulko.com>
To: Bhupesh Sharma <bhupesh.linux@gmail.com>
To: Neha Malcom Francis <n-francis@ti.com>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>
Cc: bmeng.cn@gmail.com
Cc: u-boot@lists.denx.de
Cc: u-boot-qcom@groups.io
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Changes in v3:
- Fixup patch 9
- Link to v2: https://lore.kernel.org/r/20240920-topic-ufs-enhancements-v2-0-65ae61e73eaa@linaro.org

Changes in v2:
- Added review and tested-by tags
- Updated patch 12 message with more explanations
- Synced patch 9 again with Linux 6.11
- Updated patches 7, 8, 9 and 10 with informations about the origins of the changes
- Link to v1: https://lore.kernel.org/r/20240910-topic-ufs-enhancements-v1-0-3ee0bffacc64@linaro.org

---
Bhupesh Sharma (5):
      ufs/ufs.h: Add definition of 'ufshcd_rmwl()'
      ufs: Clear UECPA once due to LINERESET has happened during LINK_STARTUP
      ufs: Sync possible UFS Quirks with Linux UFS driver
      ufs: Add missing memory barriers
      ufs: Fix debug message in 'ufs_start'

Marek Vasut (2):
      ufs: Add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS
      ufs: Add UFSHCD_QUIRK_HIBERN_FASTAUTO

Neil Armstrong (6):
      ufs: allocate descriptors with size aligned with DMA_MINALIGN
      ufs: fix dcache flush and invalidate range calculation
      ufs: split flush and invalidate to only invalidate when required
      ufs: use dcache helpers for scsi_cmd data and only invalidate if necessary
      ufs: core: remove link_startup_again logic
      MAINTAINERS: Add myself to the list of UFS maintainers

 MAINTAINERS       |   1 +
 drivers/ufs/ufs.c |  98 +++++++++++++++-----------
 drivers/ufs/ufs.h | 203 ++++++++++++++++++++++++++++++++++++++++++++++++------
 3 files changed, 241 insertions(+), 61 deletions(-)
---
base-commit: ddbcafeb53e7093c58488596bfce6d8823777c3a
change-id: 20240910-topic-ufs-enhancements-fe8ef9ce39d8

Best regards,

ufs: enhancements to support Qualcomm UFS controllers

This serie regroups all the fixes and base enhancements required to
support the Qualcomm UFS controllers in U-Boot.

This syncs headers & defines from Linux, and includes 2 set of
fixes that were sent separately:
- ufs: core: remove link_startup_again logic
- ufs: properly fix cache operations

Without those 2 sets, UFS cannot initialize on Qualcomm controlers
since v5, and a numerous of Cache issues makes any UFS controller
fail to initialize.

Since UFS core hasn't changed for a while, and since UFS is core
technology for the Qualcomm SoCs, I volunteer maintaininig the
UFS subsystem if Bhupesh & Neha Malcom Francis are ok with that.

It has been reported to show regressions on:
- TI K3 platforms (j721s2, j721e, j7200, j784s4) [1]
- AMD platform (amd_versal2_virt_defconfig) [2]

[1] https://lore.kernel.org/all/38f599a8-7094-4a04-8ff6-96fc8b9d168a@ti.com/
[2] https://lore.kernel.org/all/SA1PR12MB869713CA620F99077B75EF0E98632@SA1PR12MB8697.namprd12.prod.outlook.com/

To: Tom Rini <trini@konsulko.com>
To: Bhupesh Sharma <bhupesh.linux@gmail.com>
To: Neha Malcom Francis <n-francis@ti.com>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>
Cc: bmeng.cn@gmail.com
Cc: u-boot@lists.denx.de
Cc: u-boot-qcom@groups.io
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

---
Changes in v2:
- Added review and tested-by tags
- Updated patch 12 message with more explanations
- Synced patch 9 again with Linux 6.11
- Updated patches 7, 8, 9 and 10 with informations about the origins of the changes
- Link to v1: https://lore.kernel.org/r/20240910-topic-ufs-enhancements-v1-0-3ee0bffacc64@linaro.org

---
Bhupesh Sharma (5):
      ufs/ufs.h: Add definition of 'ufshcd_rmwl()'
      ufs: Clear UECPA once due to LINERESET has happened during LINK_STARTUP
      ufs: Sync possible UFS Quirks with Linux UFS driver
      ufs: Add missing memory barriers
      ufs: Fix debug message in 'ufs_start'

Marek Vasut (2):
      ufs: Add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS
      ufs: Add UFSHCD_QUIRK_HIBERN_FASTAUTO

Neil Armstrong (6):
      ufs: allocate descriptors with size aligned with DMA_MINALIGN
      ufs: fix dcache flush and invalidate range calculation
      ufs: split flush and invalidate to only invalidate when required
      ufs: use dcache helpers for scsi_cmd data and only invalidate if necessary
      ufs: core: remove link_startup_again logic
      MAINTAINERS: Add myself to the list of UFS maintainers

 MAINTAINERS       |   1 +
 drivers/ufs/ufs.c |  98 ++++++++++++++++-----------
 drivers/ufs/ufs.h | 199 ++++++++++++++++++++++++++++++++++++++++++++++++------
 3 files changed, 239 insertions(+), 59 deletions(-)
---
base-commit: 24961c0e0444d3ed534ffc6a173e6ea636ca116b
change-id: 20240910-topic-ufs-enhancements-fe8ef9ce39d8

Best regards,