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Abel Vesa
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Bryan O'Donoghue
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Krzysztof
krzysztof.kozlowski
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Srini Kandagatla srinivas.kandagatla
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Stephan Gerhold stephan.gerhold
- Dec 01, 2023
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Abel Vesa authoredThe SMB2360 PMICs contain the same eUSB2 repeater as the PM8550B, so add dedicated compatible for SMB82360. Signed-off-by:Abel Vesa <abel.vesa@linaro.org>
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Abel Vesa authored
Add the X1E80100 to the list of supported PHYs for eUSB2 SNPS driver. Signed-off-by: -
Abel Vesa authored
The Qualcomm X1E80100 platform has a number of eDP and DP PHY instances, add support for these. Co-developed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by:
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Abel Vesa authored
A new SoC bumps up the HW version of QMP phy to v7 for USB and PCIE. Add the new qserdes TX RX offsets in a dedicated header file. Signed-off-by: -
Abel Vesa authored
There is a variant of V6 offsets that are different and it is found QMP PHY N4. Signed-off-by: -
Abel Vesa authored
A new SoC bumps up the HW version of QMP phy to v7 for USB and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: -
Abel Vesa authored
A new SoC bumps up the HW version of QMP phy to v7 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: -
Abel Vesa authored
A new SoC bumps up the HW version of QMP phy to v7 for USB, and PCIE. Add the new PCS offsets in a dedicated header file. Signed-off-by: -
Abel Vesa authored
These new ones will be used by upcomming Qualcomm platforms. Signed-off-by: -
Abel Vesa authored
Add some missing V6 registers offsets that will be used later on by other platforms. Signed-off-by: -
Abel Vesa authored
Add the X1E80100 compatible to the list of supported PHYs. Signed-off-by: -
Abel Vesa authored
Add a dt-bindings compatible string for the Qualcomm's SMB2360 PMIC. Signed-off-by: -
Add the camcc clock driver for x1e80100 Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by:
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Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by:
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Abel Vesa authored
The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: -
Add Graphics Clock Controller (GPUCC) support for X1E80100 platform. Signed-off-by:
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Add the dispcc clock driver for x1e80100. Signed-off-by:
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Add bindings documentation for the X1E80100 Camera Clock Controller. Signed-off-by:
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Add bindings documentation for the X1E80100 Graphics Clock Controller. Signed-off-by:
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Add bindings documentation for the X1E80100 Display Clock Controller. Signed-off-by:
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Abel Vesa authored
Add bindings documentation for the X1E80100 TCSR Clock Controller. Co-developed-by:
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Abel Vesa authored
Add all missing nodes for the X1E80100 CRD reference device. Co-developed-by:
Sibi Sankar <quic_sibis@quicinc.com> Co-developed-by:
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- Nov 29, 2023
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Add the necessary dt nodes for gpu support in X1E80100. Signed-off-by:
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Abel Vesa authored
Add all missing nodes which describes entire X1E80100 platform. Co-developed-by:
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Abel Vesa authored
Add nodes for SMB2360 in separate dtsi file. Also add the eUSB2 repeater nodes. Signed-off-by: -
Enable GCC, Pinctrl and Interconnect configs for Qualcomm's X1E80100 SoC which is required to boot X1E80100 QCP/CRD boards to a console shell. The configs are required to be marked as builtin and not modules due to the console driver dependencies. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add basic support for X1E80100 CRD board dts, which allows it to boot to a shell. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers, geni UART, interrupt controller, TLMM, reserved memory, interconnects, SMMU and LLCC nodes. Co-developed-by:
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Document the X1E80100 SoC binding and also the boards using it. Also document the new board id qcp (Qualcomm Compute Platform). Signed-off-by:
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These are the CPU cores in Qualcomm's X1E80100 SoC. Signed-off-by:
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Document scm compatible for X1E80100 SoCs. Signed-off-by:
Guru Das Srinagesh <quic_gurus@quicinc.com> Reviewed-by:
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Add the SoC specific compatible for X1E80100 implementing arm,mmu-500. Signed-off-by:
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Add LLCC configuration data for X1E80100 SoC. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Add the compatible for X1E80100 platforms. Signed-off-by:
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Adds the RPMH clocks present in X1E80100 SoC Co-developed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Add bindings and update documentation for clock rpmh driver on X1E80100 SoCs. Signed-off-by:
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Add support for the global clock controller found on X1E80100 based devices. Co-developed-by:
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Add device tree bindings for global clock controller on X1E80100 SoCs. Signed-off-by:
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Stephen Rothwell authored
Signed-off-by:Stephen Rothwell <sfr@canb.auug.org.au>
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