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- Dec 01, 2023
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Abel Vesa authoredAdd definitions for the display hardware used on the Qualcomm X1E80100 platform. Co-developed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by:
Abel Vesa <abel.vesa@linaro.org>
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Abel Vesa authored
The Qualcomm X1E80100 platform has a single DisplayPort controller, with the same design as SM8550, so add support for this by reusing the SM8550 definition. Signed-off-by: -
On platforms where the endpoint used is on port@0, looking for port@1 instead results in just ignoring the max link-frequencies altogether. Look at port@0 first, then, if not found, look for port@1. Signed-off-by: -
Abel Vesa authored
Add support for MDSS on X1E80100. Signed-off-by: -
Abel Vesa authored
Add support for the SDC ATNA45AF01 panel. Signed-off-by: -
Abel Vesa authored
Add the X1E80100 DPU compatible to clients compatible list, as it also needs the workarounds. Signed-off-by: -
Add support for CPUSS Control Processor (CPUCP) mailbox controller, this driver enables communication between AP and CPUCP by acting as a doorbell between them. Signed-off-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
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Add support for PIL loading on ADSP and CDSP on X1E80100 SoCs. Signed-off-by:
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Abel Vesa authored
Add both UCSI and Battery Management support for X1E80100. Signed-off-by: -
Abel Vesa authored
Add the compatible and the driver data for X1E80100. Signed-off-by: -
Abel Vesa authored
The X1E80100 platform has two instances of the USB3 UNI phy attached to the multi-port USB controller, add definition for these. Signed-off-by: -
Abel Vesa authored
Add the X1E80100 G3 configurations. Signed-off-by: -
Abel Vesa authored
Add the X1E80100 G4 configurations. Signed-off-by: -
Abel Vesa authored
The X1E80100 has three copies of an USB/DP compbo PHY, add support for this to the Qualcomm QMP PHY driver. Signed-off-by: -
Abel Vesa authored
The SMB2360 PMICs contain the same eUSB2 repeater as the PM8550B, so add dedicated compatible for SMB82360. Signed-off-by: -
Abel Vesa authored
Add the X1E80100 to the list of supported PHYs for eUSB2 SNPS driver. Signed-off-by: -
Abel Vesa authored
The Qualcomm X1E80100 platform has a number of eDP and DP PHY instances, add support for these. Co-developed-by:
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Abel Vesa authored
A new SoC bumps up the HW version of QMP phy to v7 for USB and PCIE. Add the new qserdes TX RX offsets in a dedicated header file. Signed-off-by: -
Abel Vesa authored
There is a variant of V6 offsets that are different and it is found QMP PHY N4. Signed-off-by: -
Abel Vesa authored
A new SoC bumps up the HW version of QMP phy to v7 for USB and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: -
Abel Vesa authored
A new SoC bumps up the HW version of QMP phy to v7 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: -
Abel Vesa authored
A new SoC bumps up the HW version of QMP phy to v7 for USB, and PCIE. Add the new PCS offsets in a dedicated header file. Signed-off-by: -
Abel Vesa authored
These new ones will be used by upcomming Qualcomm platforms. Signed-off-by: -
Abel Vesa authored
Add some missing V6 registers offsets that will be used later on by other platforms. Signed-off-by: -
Abel Vesa authored
Add the X1E80100 compatible to the list of supported PHYs. Signed-off-by: -
Abel Vesa authored
Add a dt-bindings compatible string for the Qualcomm's SMB2360 PMIC. Signed-off-by: -
Add the camcc clock driver for x1e80100 Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by:
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Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by:
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Abel Vesa authored
The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: -
Add Graphics Clock Controller (GPUCC) support for X1E80100 platform. Signed-off-by:
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Add the dispcc clock driver for x1e80100. Signed-off-by:
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Add bindings documentation for the X1E80100 Camera Clock Controller. Signed-off-by:
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Add bindings documentation for the X1E80100 Graphics Clock Controller. Signed-off-by:
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Add bindings documentation for the X1E80100 Display Clock Controller. Signed-off-by:
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Abel Vesa authored
Add bindings documentation for the X1E80100 TCSR Clock Controller. Co-developed-by:
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Abel Vesa authored
Add all missing nodes for the X1E80100 CRD reference device. Co-developed-by:
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- Nov 29, 2023
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Add the necessary dt nodes for gpu support in X1E80100. Signed-off-by:
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Abel Vesa authored
Add all missing nodes which describes entire X1E80100 platform. Co-developed-by:
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Abel Vesa authored
Add nodes for SMB2360 in separate dtsi file. Also add the eUSB2 repeater nodes. Signed-off-by: -
Enable GCC, Pinctrl and Interconnect configs for Qualcomm's X1E80100 SoC which is required to boot X1E80100 QCP/CRD boards to a console shell. The configs are required to be marked as builtin and not modules due to the console driver dependencies. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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