Bumps the github-actions group with 1 update: [actions/checkout](https://github.com/actions/checkout).


Updates `actions/checkout` from 3 to 4
- [Release notes](https://github.com/actions/checkout/releases)
- [Changelog](https://github.com/actions/checkout/blob/main/CHANGELOG.md)
- [Commits](https://github.com/actions/checkout/compare/v3...v4

)

---
updated-dependencies:
- dependency-name: actions/checkout
  dependency-type: direct:production
  update-type: version-update:semver-major
  dependency-group: github-actions
...

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>

* Publish the header for the vulkan-shader-profiler embedded reflection non-semantic instruction set

vulkan-shader-profiler is a tool based on perfetto to help vulkan
developer profil their applications.
First on the Host side using perfetto, but then using the extractor
and the runner, this tools allow to get inside about a shader using
counters (based on SPV_KHR_shader_clock)

* Update include/spirv/unified1/NonSemanticVkspReflection.h

Co-authored-by: Ben Ashbaugh <ben.ashbaugh@intel.com>

* Revert "Update include/spirv/unified1/NonSemanticVkspReflection.h"

This reverts commit 3c9c24db2949c59926bd25d777e10ab60ae2cb9c.

---------

Co-authored-by: Ben Ashbaugh <ben.ashbaugh@intel.com>

This extension allows TypeVector to have a physical pointer type
Component Type and introduces gather/scatter instructions.
It will be useful for explicitly vectorized kernels.

SPIR-V validator adjustments will be done later.

Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>

Signed-off-by: Joyce <joycebrum@google.com>

Errors were printed but did not stop processing and as a result the
related issues were not caught by CI checks.


Change-Id: I030c7ffe23a4730106a19e212895bef03b6ca456

Signed-off-by: Kevin Petit <kevin.petit@arm.com>

Specification:
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_fpga_cluster_attributes.asciidoc

Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>

Relates to the recent change in SPIRV-Registry:  https://github.com/KhronosGroup/SPIRV-Registry/pull/222

Tabs and spaces mixed on the same line. It should all be spaces.

* Headers support for new FPGAMemoryAttributesINTEL

Implementation of three new FPGAMemoryAttributesINTEL:
 - StridesizeINTEL
 - WordsizeINTEL
 - TrueDualPortIntel

Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_fpga_memory_attributes.asciidoc

* Update_1

This is needed to implement 3D Image read using unnormalised sampler.
Ref google/clspv#1202

* Add a Source Language for Slang

* Changed src lang name from SLANG to Slang

* Register Slang Compiler for SPIR-V

* Added link to slang compiler repo

LiteralFloat was introduced with FPMaxErrorDecorationINTEL, but no entry in operand_kinds corresponds to it

* Add headers for SPV_NV_displacement_micromap.

* Review feedback 1

Co-authored-by: alan-baker <alanbaker@google.com>

---------

Co-authored-by: alan-baker <alanbaker@google.com>

SecondaryViewportRelativeNV already has a version field

These can only be used with OpConstantSampler, so they are naturally
restricted from being used in places where they're not supported.

Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_cache_controls.asciidoc

* Validate enums have a sensible versions and are visible

Add version field for each eumerant.

For capabilities and instructions introduced by an extension (its
first version is "None"):
- the capability should be guarded by an extension
- the instruction should be guarded by a capability.

Other enums are presumed guarded transitiviely by use as an operand
to an instruction or another operand.

Fixes: #278, #368

* Fix capability logic, and check more cases

For capabilities, only check for lack of an extension.
If capability X lists capabilities Y and Z, those are not guards *for*
X, but rather when X is enabled it also implicitly enables Y and Z.

Also, an instruction that is *not* in a core SPIR-V version
must not be directly enabled by *both* and extension and a capability.
There are 78 existing cases that break this rule, so grandparent them
in with an allow-list.

* Add "version": "None" to enums added for a recent extension

Add it for the HostAccessQualifier enums from
SPV_INTEL_global_variable_host_access

* Add SPV_INTEL_global_variable_fpga_decorations

Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_global_variable_fpga_decorations.asciidoc

* Add SPV_INTEL_global_variable_host_access

Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_global_variable_host_access.asciidoc

* Update headers generator

* update headers after generating script

Add SPV_AMDX_shader_enqueue

Revert "Merge pull request #367 from dneto0/coop-matrix-enums-deps"

This reverts commit 124a9665, reversing
changes made to f14a663c.

Cooperative matrix enums depend on the extension

This fixes basic parsing in SPIRV-Tools.

An enum is considered invisible by SPIRV-Tools if:
  - it is not in any SPIR-V core version
  - it has no enabling capabilities
  - it has no enabling extensions

So make the new cooperative matrix enums depend on the extension,
since they are not in any core version of SPIR-V, and
don't depend on any capabilities.

Remove capabilities on cooperative matrix enums to align with specifcation

Add KHR suffix to Cooperative Matrix Operands

Signed-off-by: Kevin Petit <kevin.petit@arm.com>
Change-Id: I0303c1b16e46e77f0e7e95999c606cc75f7f0d4c

Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>

Report failures in makeHeaders

Exit the script when one of the called command fails.

Signed-off-by: Kevin Petit <kevin.petit@arm.com>

Revert "Add support for fp_max_error extension"

Signed-off-by: Kevin Petit <kevin.petit@arm.com>

Add support for fp_max_error extension