generating i8 shift amounts for things like i1024 types.  Add
an assert in getNode to prevent this from occuring in the future,
fix the buggy transformation, revert my previous patch, and
document this gotcha in ISDOpcodes.h


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plus some variations of this.  According to my auto-simplifier this occurs a lot
but usually in combination with max/min idioms.  Because max/min aren't handled
yet this unfortunately doesn't have much effect in the testsuite.


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It caused a crash in MultiSource/Benchmarks/Bullet.
Opt hit an assertion with "opt -std-compile-opts" because
Constant::getAllOnesValue doesn't know how to handle floats.

This patch added a test to reproduce the problem and a check that the
destination vector is of integer type.

Thank you Benjamin!



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the shift amounts are in a suitably wide type so that
we don't generate out of range constant shift amounts.

This fixes PR9028.


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is narrower than the shift register.  Doing an anyext provides undefined bits in
the top part of the register.


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We were previously simplifying divisions, but not right shifts!


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This fixes a FIXME in scev-aa.ll (allowing a new no-alias result) and
generally makes things more precise.


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These are just FXSAVE and FXRSTOR with REX.W prefixes.  These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.


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putchar transforms, their return values are not compatible.

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The DAGCombiner created illegal BUILD_VECTOR operations.
The patch added a check that either illegal operations are
allowed or that the created operation is legal.



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Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.

Update the ARM asm parser accordingly.



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unsigned overflow (e.g. "gep P, -1"), and while they can have
signed wrap in theoretical situations, modelling an AddRec as
not having signed wrap is going enough for any case we can 
think of today.  In the future if this isn't enough, we can
revisit this.  Modeling them as having NUW isn't causing any
known problems either FWIW.


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unsigned overflow (e.g. due to a negative array index), but
the scales on array size multiplications are known to not
sign wrap.


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on the host OS.  Reviewed by dgregor.


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This avoids moving each element to the integer register file and calling __divsi3 etc. on it.


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that the condition is not a vector.



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Add more folding patterns to constant expressions of vector selects and vector
bitcasts.



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Fix #9190

The bug happens when the DAGCombiner attempts to optimize one of the patterns
of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
on 32bit machines, but the initializer of this vector (i64) is target dependent.
Currently, the initializer attempts to create an i64 zero constant, which fails.
Added a flag to tell the DAGCombiner to create a legal zero, if we require that
the pass would generate legal types.



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objects, since they'll end up using the implicit conversion to "bool"
and causing some very "fun" surprises.


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a loop when unswitching it. It only does this in the complex case, because
everything should be fine already in the simple case.

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