added check for port num and channel iteration are lessthan 8
to avoid out of bound write to 8x8 map array.

Change-Id: I4c6fe13a5eb09be623a1c40ce16c5a5e4246e021
Signed-off-by: Abinath S <quic_abins@quicinc.com>

Change-Id: I9e69f887d0b11dd6d46086630a7ee053d3cb3f3d

Change-Id: I4c28d8f3bdf25e12116af8211b34eb1c20be0b5a

If qcom,wcd-disabled node is defined in DT, then
msm_rx_tx_codec_init returns without updating WSA
port config. This causes a NULL pointer dereference
later during playback use-case when port params are
accessed. Hence, update the WSA/WSA2 port config
before exiting msm_rx_tx_codec_init.

Change-Id: I9b05d4d707c297470614d94a7637d4f883b4b599
Signed-off-by: Hanuma Sri Saketh Valluri <quic_sakevall@quicinc.com>

Change-Id: Ib619f003cdd4d052a9947bdf73620203504508f9
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
(cherry picked from commit eac8dc64)

Unmute WSA after enabling main path for
ADIE loopback cases.

Change-Id: I850aa4dbcf77371811010c1d614c6c7e94736971
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
(cherry picked from commit 2c2db127)

it is possible that gpr may get deregistered already and
hence will not get any pointer for gpr from dev_get_drvdata
so proceed further only if gpr exists otherwise,
it will lead to crash issue.

Change-Id: I4129a76d1deade0c243c9a9515a8f84542f3596c
(cherry picked from commit 8b989e69)

As part of the mute stream enable PA and VI decimator
for AIF1 and AIF_mix1 dai id's
Change-Id: I1f5d9a3692a1ece6393c8fa53d6faec64abc2675

Unmute digital volume after analog PA is enabled to reduce
pop issues.

Change-Id: Iae4a5b6df3c258e1ab9976bb0a47946c5a681b08

FIFO_Flush should only be for SWRM_INTERRUPT_STATUS_CMD_ERROR.
For other usecase, it should not be flushed otherwise it would
cause register write mismatch and cause some sideeffect.

Change-Id: I6d40a30129dfdf48993125fb57042ab97a13a631
Signed-off-by: Meng Wang <quic_mengw@quicinc.com>

Change for not increasing the active_channel_count value if the mixer
control corresponding to the Dec is already set.

Change-Id: Iad2e513f16bbe2768ff302f72bd9a5af31042b4b
Signed-off-by: Pratyush Meduri <quic_mpratyus@quicinc.com>

During some concurrencies even though we are not
enabling the swrm port, we are trying to disable it.
which causes problem w.r.t clock disablement,
To avoid that we are updating the set bit only
when port is enabled, based on that bit we are taking
decision to disable or enable the port.

Change-Id: Iac9769515e17a228e31eebb052d1efac313e679d
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>

During swr disconnect port, swr master num port is
updated based on the portinfo we receive from slave.
Instead update the master num port based on the ports
enabled. and also if requested port is not enabled
continue to check for other enable port instead of
returning error.

Change-Id: I29a1c1fdbd66eb4a244effe608f79f7b67eb9c3c
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>

This reverts commit b8371207.

Change-Id: Ie5929b54960e68187b71f7bf997039bdf80eaaa0

Add wcd_disabled check in late_probe to avoid checking
wcd component when WCD is disabled

Change-Id: I0de73a09f1bdfffac1412a4c1f8f8ec5e64e4c4b
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>

reset analog and digital path clk ctrl registers,also analog Tx path
configuration only when no active ADC.

Otherwise mute observed for Tx path when these common registers are reset
as part of powering down of any ADC, which is still needed by other
active ADC.

Change-Id: Ic8bc4c2c150205daa4973d800b5b2a7b67c4c6da
Signed-off-by: Shalini Manjunatha <quic_c_shalma@quicinc.com>

Add ioctl support for 32 bit userspace on 64bit platform.

Change-Id: I8e73d4fa975cc7562c8404639f30fb3d0f31f4a9

add lock in ion free to protect dma buff and avoid
use after free.

Change-Id: I6376408ce1a5b98b7aeacc32e44ec4db08ff9df5
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>

During spk playback and VA concurrency,
sometimes WSA CLK goes out of sync causing
VI_TX data mute. To resolve this, everytime
after WSA MCLK enable toggle fs_cnt_clr bit.

Change-Id: Ia936f1d4843890d2ae5c02b039f502941a5427b9
Signed-off-by: Soumya Managoli <quic_c_smanag@quicinc.com>

While graph_open is processing by the SPF, apps receives
userspace(agm/pal) crash which will triggers spf_close_all
cmd from msm common drivers and immediately calls
msm_audio_ion_crash_handler() which will un-maps the memory. But
here SPF is still in processing the graph_open, recieved spf_close_all
cmd is queued in SPF. Due to un-mapping is done immediately in HLOS
will resulting in SMMU fault.

To avoid such scenarios, increased the spf_close_all cmd timeout,
because the AGM timeout for the graph_open is 4sec, so increase the timeout
for spf_close_all cmd response until graph open completes or timed out.

Change-Id: I67430cad5a55bd250ea110587c0ead2d97115efc
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>

Enable the VI decimator at the end of Rx and VI enable sequence

Change-Id: I12045c903b29d4cc830dbbfd242d805a629c0efd
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>

Currently, 0 is written into SWR_PLAY register when disabling SWR play,
it coincidently updates the PLAY_SRC to FIFO mode and disables it. If
there is a FIFO play triggered from SPMI address space, the FIFO play
will be disabled and the FIFO samples will be flushed. To avoid this,
keep in SWR PLAY_SRC when disabling SWR play.

Change-Id: Ib594df57835979a8832f2f7a1954ff36f643f724
Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>

as part of swrm_runtime_suspend, multiple attempts are made
to write into swr regisers. Incase of SSR state, all those write
 attempts are bound to fail.
Hence avoid swr read/write operations during SSR state.
Also move updating dev_up flag for SSR event to an early point in call flow.

Change-Id: I805d1ccf8bcdab5fdde7b74582a65463d5bcbd6e
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>

enable the wsa and wsa2 clk as per sequence.

Change-Id: Ieefa4b6ea7aec535d940d780b0ed923483b4d3ee
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>

Update sample interval for class-H port to 64 so that the
class-H code is sent to WCD correctly over soundwire bus

Change-Id: Id05853a25e97d9a39452722c7959e08bc9651e0b
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>

Enable the clk as per sequence.

Change-Id: I54d6981a70b218d4655514bb69ff39a7581264a2
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>

Update ch_msk and audio path for VI feedback path
in lpass_wsa2 macro.

Change-Id: I951e0ab88d194da39d8718491b9dbe9d008a2c0f

Update status of WSA883X_IRQ_INT_PDM_WD interrupt and
check for its status before enabling/disabling to
avoid unbalenced interrupt condition.

Change-Id: I45b400fd03668d892f09fb653f493fc726f67bc3
Signed-off-by: Puneeth Prabhu <quic_pprabh@quicinc.com>