asoc: Enable SWR port mapping for VI sense

Add new table rx_frame_params_visense under
swr port config to support VI data.
Change register sequence for reg_init for VI sense
same as A+S variant.
Support parsing of visense-support dt entry by
besbev node instead of machine driver node.
Populate valid initial temp val if OTP registers
read value is OTP invalid.

Change-Id: I420ae668da68998170f7ebc23fbffe152d23bdde
Signed-off-by: Ashish Kumar <quic_ashik@quicinc.com>
(cherry picked from commit 2cdcac2d)