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Mahadevan authored
The issue is as follows: Commit N: 1. VIG sspp qseed block programmed through lutdma. LUTDMA packet with (ram offset, length_0) is queued to internal HW queue to enable scaler. 2. Input_fence timeout seen on VIG plane. 3. White color solid fill layer staged on VIG plane. 4. Disable VIG sspp qseed block through LUTDMA. LUTDMA packet is queued by overriding buffer with (ram offset, length_1) to internal HW queue to disable scaler. 5. Trigger_flush is picked by HW on vsync. Since 2 LUTDMA packets are queued on single vsync boundary pp_done timeout with lutdma HW hang is seen. The only way to fix this is to reset LUTDMA in step4 and then flush the Hardware. The current SW does not support this reset sequence, so the change avoids staging solid fill on input fence timeout. Change-Id: Ia243e42c863f56b11bee5aeed2dd434efcbd5d75 Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
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