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createMachineVerifierPass and MachineFunction::verify.

The banner is printed before the machine code dump, just like the printer pass.

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The result vector elements are always integers.  Radar 8782191.

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interference.

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RegAllocBase::VerifyEnabled.

Run the machine code verifier in a few interesting places during RegAllocGreedy.

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The heuristics split around the largest loop where the current register may be
allocated without interference.

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Add vector versions of some existing scalar transforms to aid codegen in matching psign & pblend operations to the IR produced by clang/gcc for their C idioms.


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may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.

Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)

<rdar://problem/8782198>


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BUILD_VECTOR operands where the element type is not legal.  I had previously
changed this code to insert TRUNCATE operations, but that was just wrong.

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The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

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Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts


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monotonic keys.

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moves the iterator to end(), and it is valid to call it on end().

That means it is valid to call advanceTo() with any monotonic key sequence.

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Thumb's forced-PC-alignment requirement applies to the _total_ displacement, not just to the fragment relative
portion.  While the fragment boundary is usually already aligned, it is possible for it not to be, which 
would lead to a non-aligned final displacement.


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code for the case where 32-bit divide by constant is
turned into 64-bit multiply by constant.  8771012.



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the operand uses the same register as a tied operand:

  %r1 = add %r1, %r1

If add were a three-address instruction, kill flags would be required on at
least one of the uses. Since it is a two-address instruction, the tied use
operand must not have a kill flag.

This change makes the kill flag on the untied use operand optional.

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a partial value. rdar://8782954

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Reapply r121905 (automatic synthesis of @llvm.sadd.with.overflow) with a fix for a bug that manifested itself
on the DragonEgg self-host bot.  Unfortunately, the testcase is pretty messy and doesn't reduce well due to
interactions with other parts of InstCombine.


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Patch (slightly modified) by Visa Putkinen.


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