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sarl    $3, %ecx

instead of:

movl    $3, %ecx
sarl    %cl, %edx

This shrinks fast isel 176.gcc by about 2000 instructions (.3%)



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Handle{Virt,Phys}Reg{Def,Use}. Remove a redundant check
for register zero, and redundant checks for isPhysicalRegister.


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compute the maximum element directly.


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correct in the presence of things like EH labels.


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Change some class to struct for coherency.

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Per review feedback.



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of mayReadFromMemory and mayWriteToMemory.


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Check bits for preferred register.



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Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.


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results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.


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have previously been assigned conflicting physreg.



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use ARG_FLAGSSDNode as the most aligned node type,
as it contains an int64_t, which is 8-byte
aligned on mingw.


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untested, Use::swap() is definitely not done yet

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and non-demotion of readnone to readonly.


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Unfortunately this means removing one regression test
of GlobalsModRef because I couldn't work out how to
perform it without MarkModRef.


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can get the readnone/readonly attributes, and gives them it.
The plan is to remove markmodref (which did the same thing
by querying GlobalsModRef) and delete the analogous
functionality from GlobalsModRef.


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description says it does), not just when -analyze is
used as well.  This means printing to stderr, so adjust
some tests.


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and redo as linked list walk.  Logic moved into RA.
Per review feedback.



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Fixes PR 2805


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catches a fair number of common cases. Note that this currently
causes Fast-ISel to leave behind lots of dead instructions.
Those will be dealt with in subsequent commits.


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Thanks to Ji Young Park for the patch!


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