Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
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- lib/Target/ARM/AsmParser/ARMAsmParser.cpp 8 additions, 4 deletionslib/Target/ARM/AsmParser/ARMAsmParser.cpp
- test/CodeGen/ARM/inlineasm3.ll 1 addition, 1 deletiontest/CodeGen/ARM/inlineasm3.ll
- test/MC/ARM/neon-vld-encoding.s 71 additions, 62 deletionstest/MC/ARM/neon-vld-encoding.s
- test/MC/ARM/neon-vst-encoding.s 51 additions, 44 deletionstest/MC/ARM/neon-vst-encoding.s
- test/MC/ARM/neont2-vld-encoding.s 24 additions, 24 deletionstest/MC/ARM/neont2-vld-encoding.s
- test/MC/ARM/neont2-vst-encoding.s 21 additions, 21 deletionstest/MC/ARM/neont2-vst-encoding.s
- test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt 1 addition, 1 deletion.../MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
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