Record SCU wakeup interrupt in /sys/power/pm_wakeup_irq
The user can further identify the exact wakeup source by using the
following interface:
cat /sys/firmware/scu_wakeup_source/wakeup_src

The above will print the wake groups and the irqs that could have
contributed to waking up the kernel. For example if ON/OFF button was the
wakeup source:
cat /sys/firmware/scu_wakeup_source/wakeup_src
Wakeup source group = 3, irq = 0x1

The user can refer to the SCFW API documentation to identify all the
wake groups and irqs.

Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
(cherry picked from commit d49daabf)

Since IRQF_NO_SUSPEND used for imx mailbox driver, that means this irq
can't be used for wakeup source so that can't wakeup from freeze mode.
Add pm_system_wakeup() to wakeup from freeze mode.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit d12a9c62)

Change enable calls to disable calls in imx8qm_ipg_clk_disable

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>

This fixes an issue where there is no display after resuming from suspend
due to missing PHY initialization.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>

Since CPU clocks are managed by CPUFREQ, do not enable
runtime PM otherwise rpm gets out of status as cpufreq
also manages clock states.

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
(cherry picked from commit e28b1ba0)
(cherry picked from commit 813a21285eca606aca805f1ac3aabe09e9f4e346)

after get v2x reset event, return error at read
v2x reset after system enter ks1.

Signed-off-by: Frank Li <Frank.Li@nxp.com>

When the crash of a remote proc is detected, the physical communication
channels may get corrupted or reset, and it will impact the subsequent
transfers of rpmsg message. So the communication channels should be
re-built when a remote crash is detected.

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>

Current workaround is looping uselessly on the address
range doing a  _tlbi(vmalle1is) which is harmful for
the system performance and buggy as the instruction is
flushing the entire TLB and there is no benefit of
redoing it more than once. Also fix missing barriers.

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
(cherry picked from commit 5799755f37dd7bc826dfe8a3cac12871a7946a1a)

When booting with lcdif dtb file, the pca6416_3 interrupt controller
keeps sending interrupts that are not handled by anyone. Apparently this
was caused by the removal of some pinctrls unrelated to LCDIF, when
removing the pinctrl for IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1.
In order to fix this, add those pinctrls back, so that only the
definition for IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 is overwritten.
Also, remove the disabling of lpspi3, since that node doesn't have any
conflict with LCDIF.

Fixes: 6024c8cb ("arch: arm64: dts: im8dxl: add lcdif dts file")
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>

Use "fsl,imx-audio-ak5552" compatible in AK5552 audio card node
in order to enforce proper constraints on number of channels.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 7075d4f1698c5c95f0c382c8a2000b8999a39176)

SAI3 is used for RX only and is bound to AK5552 codec.
Thus ensure SAI3 RX is not in sync with TX so that
the proper RX CFG2 register is programmed.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 34ec2e74990d569868ba941d535cf9e66e9c0281)

Sometimes the codec is probed before the GPIO
controller is available. This leads to annoying
EPROBE_DEFER related log, so fix this.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 2a3ab6de8f1ae561996e7613d340c46749704151)

The CORE/BUS root slice has following design, simplied graph:
The difference is core not have pre_div block.
A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].

It support target(smart) interface and normal interface. Target interface
is exported for programmer easy to configure ccm root. Normal interface
is also exported, but we not use it in our driver, because it will
introduce more complexity compared with target interface.

The normal interface simplified as below:
            SEL_A  GA
            +--+  +-+
            |  +->+ +------+
CLK[0-7]--->+  |  +-+      |
       |    |  |      +----v---+    +----+
       |    +--+      |pre_diva+---->    |  +---------+
       |              +--------+    |mux +--+post_div |
       |    +--+      |pre_divb+--->+    |  +---------+
       |    |  |      +----^---+    +----+
       +--->+  |  +-+      |
            |  +->+ +------+
            +--+  +-+
            SEL_B  GB

The mux in the upper pic is not the target interface MUX, target
interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7],
you are actually writing SEL_A or SEL_B depends on the internal
counter which will also control the internal "mux".

The target interface simplified as below which is used by Linux Kernel:
CLK[0-7]--->MUX-->Gate-->pre_div-->post_div

A requirement of the Target Interface's software is that the
target clock source is active, it means when setting SEL_A, the
current input clk to SEL_A must be active, same to SEL_B.

We touch target interface, but hardware logic actually also need
configure normal interface.

There will be system hang, when doing the following steps:
The initial state:
  SEL_A/SEL_B are both sourcing from clk0, the internal counter
  choose SEL_A.
1. switch mux from clk0 to clk1
   The hardware logic will choose SEL_B and configure SEL_B to clk1.
   SEL_A no changed.
2. gate off clk0
   Disable clk0, then the input to SEL_A is off.
3. swtich from clk1 to clk2
   The hardware logic will choose SEL_A and configure SEL_A to clk2,
   however the current SEL_A input clk0 is off, the system hang.

The solution to fix the issue is in step 1, write twice to
target interface MUX, it will make SEL_A/SEL_B both sources
from clk1, then no need to care about the state of clk0. And
finally system performs well.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

ISI core driver depend on soc version info but driver provided the info
is not ready when ISI core driver probe, so return -EPROBE_DEFER replaced
with -EINVAL.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>

There are some corner cases that system may hang when do suspend/resume.
"
[   55.692047] dwhdmi-imx 32fd8000.hdmi: calling genpd_suspend_noirq+0x0/0x18 @ 590, parent: 32c00000.bus
[   55.701376] dwhdmi-imx 32fd8000.hdmi: genpd_suspend_noirq+0x0/0x18 returned 0 after 17 usecs
[   55.709824] imx-irqsteer 32fc2000.irqsteer: calling pm_runtime_force_suspend+0x0/0xd0 @ 590, parent: 32c00000.bus
hang....
"

It is because hdmi root clk is disabled. In our current code
implementation, we assume to access registers with only hdmi apb clk
enabled. In our suspend test, we see cases that
hdmi root gate clk is disabled, hdmi apb clk is enabled, but system
still hang. So Per test, we need hdmi root clk also be enabled to
access registers.

Considering the complexity of enabling hdmi root clk to clk-hdmimix.c,
we directly add the power-domains property to irqsteer hdmi node. The
power domain driver handled the clk and the irqsteer driver support
runtime pm. So take simple workaround, add property
"power-domains = <&hdmimix_pd>;" to irqsteer hdmi node.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

For some tough multi channels test, the default priority of channel0 may
not be scheduled in 500us so that channel context can't be loaded as the
below warning, hence sdma channel transfer will be failed. So raise up
channel0 to the highest one since context load is important to all
channels. Besides, enlarge 500us to 5ms for safe since many highest channel
also may run at the same time like asrc/easrc tough test(8 channel run).

"imx-sdma 30e10000.dma-controller: Timeout waiting for CH0 ready"

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Peng Zhang <peng.zhang_8@nxp.com>
(cherry picked from commit 41fdb664)
(cherry picked from commit 59c8c5cbe60112f87ae97e5b6ead88c049b5d89b)

Since mmap for userspace is based on page alignment, add page alignment
for iram alloc from pool, otherwise, some good data located in the same
page of dmab->area maybe touched wrongly by userspace like pulseaudio.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit a2664972a18021d6f336922f511f39442b8458e2)

check iram_pool before sdma_init_sw() so that ccb/context could be
allocated from iram because DDR maybe in self-referesh in lower power
audio case while sdma still running.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 6087a1b040c7df054efefd6eda7c031b49b80276)

Save iram pool bd allocated in in i.mx6sll low power audio playback case,
including below refine points:
  1. corrected to bd_size instead of page size for iram pool case.
  2. use common DDR memory instead of iram for script loading.
  3. channel0 also down to 1 bd size instead of page size.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 0cc37c475172c5d91c20380acd737e198f8986ff)

ENABLE_M4 should be set to 1 when loading code to TCM, otherwise
you will not able to replace the firmware after you stop m4.

Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Remove reserved memory for isp1 because now only use one isp0 for tuning tool.
The reserved memory is only used for tuning tool, could be removed for normal
operations.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: G.n. Zhou <guoniu.zhou@nxp.com>

Add explict memory barrier for the wdog unlock sequence.

Suggested-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

commit f232326f upstream.

The purpose of this patch is to streamline error propagation and in particular
to propagate retrieve_ptr_limit() errors for pointer types that are not defining
a ptr_limit such that register-based alu ops against these types can be rejected.

The main rationale is that a gap has been identified by Piotr in the existing
protection against speculatively out-of-bounds loads, for example, in case of
ctx pointers, unprivileged programs can still perform pointer arithmetic. This
can be abused to execute speculatively out-of-bounds loads without restrictions
and thus extract contents of kernel memory.

Fix this by rejecting unprivileged programs that attempt any pointer arithmetic
on unprotected pointer types. The two affected ones are pointer to ctx as well
as pointer to map. Field access to a modified ctx' pointer is rejected at a
later point in time in the verifier, and 7c696732 ("bpf: Permit map_ptr
arithmetic with opcode add and offset 0") only relevant for root-only use cases.
Risk of unprivileged program breakage is considered very low.

Fixes: 7c696732 ("bpf: Permit map_ptr arithmetic with opcode add and offset 0")
Fixes: b2157399 ("bpf: prevent out-of-bounds speculation")
Signed-off-by: Piotr Krysiuk <piotras@gmail.com>
Co-developed-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

MIPI1 and LVDS1 should be enabled in the HDMI configuration.
Added DP configuration for MEK board.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>

The power off needs to be called in remove to keep the correct clock
enable counts.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>

The power off need to be handled for the remove case so the
clock enable counts are correct.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>

Port the i2c over aux feature from 4.19.35 to the 5.4.x kernel. Add the
the i2c read/write functions. The i2c features in the FW have been introduced in
version 1.0.62.

Signed-off-by: Julien Jayat <julien.jayat@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>

Disable the L1SS feature in default.
Please remove this patch, if L1SS is required, and make sure
that the HW supports L1SS.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
(cherry picked from commit 2843e1e62c991aab16150a56508d415fd43f3fbc)

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
(cherry picked from commit 94e84f467b688ce79eb3239f1516f6009b75a19b)

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
(cherry picked from commit d9f9d0c73d3965e6a7b130e2b762a8ff7d4f04a7)

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
(cherry picked from commit c14681471c737280d93d1e5f83221576caf352ee)

This patch replaced link-frequencies to express single/dual cameras case, which
is introduced from 21c3114f
MLK-23600-6 Update Basler camera link-frequencies to differentiate used MIPI clock

Originally from Thies Moeller <thies.moeller@baslerweb.com>
With the fix for max-pixel-frequency for dual cameras basler camera + ov5640.

For other sensor porting, could also use max-pixel-frequency property.
Other properties might be optional.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: G.n. Zhou <guoniu.zhou@nxp.com>

Some HW boards might not support the L1.1 ASPM, although the L1.1 ASPM
is supported by the SOC chip.
So, export one property to disable L1.1 ASPM supported or not.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
(cherry picked from commit 4e42c418396d545a48a4eb47a04ce73a27b0415e)

HW board design may not support the L1.1 ASPM, although the L1.1 ASPM
can be supported by the SOC chip.
So, export one property to disable L1.1 ASPM supported or not.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
(cherry picked from commit 7bd2d56b72d33e223305aa2ef9046c0e38f225e6)

Correct one of the imx8mq_pcie1_ctrl_sels, from "sys2_pll_250m"
to "sys2_pll_333m".

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 6c34e907db3da694a63dbd44668189f769e686fe)

Since the parent clock setting had been done in dts node.
Remove the codes from clock driver.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit b4dd057204f0ba55e5ceea670b475204096e4f6c)

Specify the clock rate and parent of i.MX8MQ/MM PCIe clocks.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 5c9865f4184ad9251d147126814a36e193226aae)

dma API(s) can't use NULL device because of following patch:

d7e02a93 dma-mapping: remove leftover NULL device support

this patch uses pxp_dev instead of NULL device to resolve kernel dump.

[  445.484900] 8<--- cut here ---
[  445.488002] Unable to handle kernel NULL pointer dereference at virtual address 0000015c
[  445.512965] pgd = 2afadd37
[  445.515707] [0000015c] *pgd=00000000
[  445.521436] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
[  445.526776] Modules linked in: 8021q mx6s_capture ov5640_camera_v2
[  445.532993] CPU: 0 PID: 2117 Comm: vqueue:src Not tainted 5.4.70-2.3.0+g4f2631b022d8 #1
[  445.541006] Hardware name: Freescale i.MX6 Ultralite (Device Tree)
[  445.547214] PC is at pxp_device_ioctl+0xc64/0xe80
[  445.551933] LR is at pxp_buffer_object_lookup+0x30/0x38
[  445.557169] pc : [<80550e20>]    lr : [<8054fd00>]    psr: 60000013
[  445.563446] sp : 93bffea8  ip : 908a03ac  fp : 76957ff8
[  445.568681] r10: 00000036  r9 : 93bfe000  r8 : 93b04540
[  445.573917] r7 : 939d78c0  r6 : 80085007  r5 : 939d77c0  r4 : 00000000
[  445.580454] r3 : 00000001  r2 : 00000000  r1 : 00000002  r0 : 939d77c0
[  445.586993] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
[  445.594140] Control: 10c5387d  Table: 93bd806a  DAC: 00000051
[  445.599904] Process vqueue:src (pid: 2117, stack limit = 0xcf85841b)
[  445.606270] Stack: (0x93bffea8 to 0x93c00000)
[  445.610645] fea0:                   73800000 8020a840 93ab8800 81304f08 739bc000 93ab8800
[  445.618841] fec0: 93b8f840 739bc000 93b0fa80 8020eddc 93ab8800 00000002 00000001 00100c00
[  445.627037] fee0: 00000000 93bffee8 00000000 81304f08 00000008 741d7ff4 926428d0 80085007
[  445.635234] ff00: 741d7ff4 93b04540 93bfe000 00000036 76957ff8 80256c3c 93ab8800 0000010a
[  445.643430] ff20: 00000106 00000000 00000000 93b8f840 00000001 80210c20 000001e7 00000000
[  445.651626] ff40: 0009a100 93b8f848 93bfff54 0001c200 93bfff7c 00000001 93b04540 0000000b
[  445.659822] ff60: 00000001 00004000 93adc200 81304f08 93b04541 0000000b 80085007 741d7ff4
[  445.668019] ff80: 93b04540 93bfe000 00000036 8025716c 75742980 743caee0 01a152e0 00000036
[  445.676214] ffa0: 80101204 80101000 75742980 743caee0 0000000b 80085007 741d7ff4 743cb004
[  445.684410] ffc0: 75742980 743caee0 01a152e0 00000036 00000002 741d8064 741d81d4 76957ff8
[  445.692605] ffe0: 743caf40 741d7fd4 743b88d1 76d2cfe8 80000030 0000000b 00000000 00000000
[  445.700820] [<80550e20>] (pxp_device_ioctl) from [<80256c3c>] (do_vfs_ioctl+0x404/0x900)
[  445.708936] [<80256c3c>] (do_vfs_ioctl) from [<8025716c>] (ksys_ioctl+0x34/0x60)
[  445.716355] [<8025716c>] (ksys_ioctl) from [<80101000>] (ret_fast_syscall+0x0/0x54)
[  445.724023] Exception stack(0x93bfffa8 to 0x93bffff0)
[  445.729091] ffa0:                   75742980 743caee0 0000000b 80085007 741d7ff4 743cb004
[  445.737287] ffc0: 75742980 743caee0 01a152e0 00000036 00000002 741d8064 741d81d4 76957ff8
[  445.745477] ffe0: 743caf40 741d7fd4 743b88d1 76d2cfe8
[  445.750550] Code: e595100c e3a00000 e12fff34 eafffd39 (e594315c)
[  445.773509] ---[ end trace a4bb9353c99e0cef ]---

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: G.n. Zhou <guoniu.zhou@nxp.com>

The commit af20fa80 introduced a break when cherry-pick from mainline.

make[3]: *** No rule to make target 'arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dtb', needed by '__build'.  Stop.
make[3]: *** Waiting for unfinished jobs....
  DTC     arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dtb
make[2]: *** [../scripts/Makefile.build:500: arch/arm64/boot/dts/freescale] Error 2
make[1]: *** [/home/nxa14866/ProjectA/linux-imx_bk/Makefile:1269: dtbs] Error 2
make[1]: Leaving directory '/home/nxa14866/ProjectA/linux-imx_bk/build_v8'
make: *** [Makefile:179: sub-make] Error 2

The patch removed build for imx8mp-evk-iqaudio-dacplus.dtb because it's not in this branch.

Signed-off-by: Robby Cai <robby.cai@nxp.com>

Refine commit 17db82300f80 ("MLK-25089 phy: freescale: pcie: fix the
imx8mp evk ep rc link speed issue")
Fine tune the PHY parameters, let the PCIe link up to GEN3 between two
i.MX865 EVK boards in the i.MX EP RC validation system.

Since this fine tuned is only specified for EVK boards. Add the command
parameter to specify it when do the EP RC tests between two i.MX8MP EVK
boards. Use the "pcie_phy_tuned=yes" to enable the PHY fine-tune.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit 2ab5581a1448bf24a37f8082ffe725a54ce09b5e)