- Jun 29, 2022
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Sherry Sun authored
Enable the uart dma mode on imx6ul/imx6ul/imx6ulz platforms. Signed-off-by:
Sherry Sun <sherry.sun@nxp.com> Reviewed-by:
Jun Li <jun.li@nxp.com> Acked-by:
Jason Liu <jason.hui.liu@nxp.com>
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- Jun 28, 2022
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Sherry Sun authored
Use wait_event_interruptible in lpuart_dma_shutdown isn't a reasonable behavior, since it may cause the system hang here if the condition !sport->dma_tx_in_progress never to be true in some corner case, such as when enable the flow control, the dma tx request may never be completed due to the peer's CTS setting when run .shutdown(). So here change to use wait_event_interruptible_timeout instead of wait_event_interruptible, the tx dma will be forcibly terminated if the tx dma request cannot be completed within 300ms. Considering the worst tx dma case is to have a 4K bytes tx buffer, which would require about 300ms to complete when the baudrate is 115200. Signed-off-by:
Shenwei Wang <shenwei.wang@nxp.com> Acked-by:
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Sherry Sun authored
For the lpuart wakeup source mode, we need to make sure the system can be waken up immediately when the uart receive even one character. So set the rx_watermask to 0 directly, then UARTCTRL_ILIE interrupt is not needed any more. The rx_watermask will be set back to the original values in lpuart32_hw_setup() which will be called in system resume. Signed-off-by:
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- Jun 24, 2022
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Gaurav Jain authored
Root cause: When caam queue is full (-ENOSPC), caam frees descriptor memory. crypto-engine checks if retry support is true and h/w queue is full(-ENOSPC), then requeue the crypto request. During processing the requested descriptor again, caam gives below error. (caam_jr 30902000.jr: 40000006: DECO: desc idx 0: Invalid KEY Command). This patch adds a check to return when caam input ring is full and retry support is true. so descriptor memory is not freed and requeued request can be processed again. Fixes: 791809fd ("crypto: caam - enable crypto-engine retry mechanism") Signed-off-by:
Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by:
Horia Geantă <horia.geanta@nxp.com>
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Iuliana Prodan authored
Use the new crypto_engine_alloc_init_and_set() function to initialize crypto-engine and enable retry mechanism. Set the maximum size for crypto-engine software queue based on Job Ring size (JOBR_DEPTH) and a threshold (reserved for the non-crypto-API requests that are not passed through crypto-engine). The callback for do_batch_requests is NULL, since CAAM doesn't support linked requests. Signed-off-by:
Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Jason Liu authored
Paired with suspend, we can only init wdog again when it was active and ping it once to avoid the watchdog timeout after it resumed. Signed-off-by:
Ye Li <ye.li@nxp.com> Reviewed-by:
Jacky Bai <ping.bai@nxp.com> Tested-by:
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Jason Liu authored
According to system design, for mem low power mode, wdog1 will be reset and enabled with unlock mode by HW automatically after return from low power mode(mem mode). So, we can directly reconfigure wdog1 without follow the unlock sequence which has 16 bus cycles constrains. The safe way is to disable wdog1 after resume from low power mode(mem), which can avoid the watchdog timeout before watchdog driver resume. This fixes the suspend/resume stress test with overnight stress test. For standby mode,no action need taken as wdog will not reset and driver will stop it during driver supsend. The wdog driver will resume watchdog function and enable it accordingly. Signed-off-by:
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- Jun 20, 2022
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Gaurav Jain authored
issue: when bus frequency set to low, error reported duing hwrng operation. "Busfreq OPTEE set from 533000000 to 24000000 start..." "Busfreq OPTEE set to 24000000 done! cpu=0" "caam_jr 30902000.jr: 2000005b: CCB: desc idx 0: RNG: Hardware error" fix: TRNG configuration fails to work with low bus frequency(24Mhz). so request high bus frequency before hwrng operation start and release high bus frequency after completion of hwrng operation. Signed-off-by:
Varun Sethi <V.Sethi@nxp.com> Signed-off-by:
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Sandor Yu authored
Currently, mipi dsi and lcdif pixel clock use default parent clocks that setting in uboot. Drivers will fail to work when uboot setting changed. Assign their parent clocks to avoid such issue. Signed-off-by:
Sandor Yu <Sandor.yu@nxp.com> Reviewed-by:
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- Jun 06, 2022
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Dong Aisheng authored
There's a potential A-B/B-A deadlock between Clock and PM domain framework in current kernel. Accessing PD clocks in genpd->power_on()/ power_off() callback is unsafe as mentioned in the commit 2b31e22d5376 ("PM: domains: add pm domain clocks support"). This patch switches to use the in core GENPD_FLAG_PM_PD_CLK feature for imx8mp only to avoid such possible deadlock issue. Signed-off-by:Dong Aisheng <aisheng.dong@nxp.com> (cherry picked from commit b1f1595f) Acked-by:
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Dong Aisheng authored
Both blkctl clocks and resets support runtime pm. Async pm_runtime_put of reset devices may cause a SW lockup (waiting for RPM_SUSPENDING/RESUMING finish) on the same blkctl device runtime pm state when both reset and clk are used by different consumer devices. This patch fix below possible SW lockup: [ 62.673341] task:kworker/0:1 state:D stack: 0 pid: 10 ppid: 2 flags:0x00000008 [ 62.681758] Workqueue: pm pm_runtime_work [ 62.685815] Call trace: [ 62.688300] __switch_to+0x154/0x1b0 [ 62.691913] __schedule+0x2f0/0x990 [ 62.695440] schedule+0x74/0x110 [ 62.698683] schedule_preempt_disabled+0x28/0x44 [ 62.703341] __mutex_lock+0x2f8/0x474 [ 62.707040] mutex_lock_nested+0x3c/0x6c [ 62.711006] clk_prepare_lock+0x48/0xac [ 62.714877] clk_unprepare+0x28/0x50 [ 62.718465] clk_bulk_unprepare+0x3c/0x60 [ 62.722514] pm_genpd_disable_clks+0x64/0x74 [ 62.726842] genpd_runtime_suspend+0x1f8/0x250 [ 62.731323] __rpm_callback+0x48/0x140 [ 62.735112] rpm_callback+0x6c/0x80 [ 62.738613] rpm_suspend+0x10c/0x62c [ 62.742232] pm_runtime_work+0xc8/0xcc [ 62.746020] process_one_work+0x288/0x6d4 [ 62.750066] worker_thread+0x78/0x464 [ 62.753767] kthread+0x158/0x164 [ 62.757033] ret_from_fork+0x10/0x20 [ 62.894459] Workqueue: events_unbound deferred_probe_work_func [ 62.900341] Call trace: [ 62.902795] __switch_to+0x154/0x1b0 [ 62.906412] __schedule+0x2f0/0x990 [ 62.909944] schedule+0x74/0x110 [ 62.913218] rpm_resume+0x160/0x6e0 [ 62.916748] __pm_runtime_resume+0x40/0x90 [ 62.920890] clk_pm_runtime_get.part.0+0x20/0x90 [ 62.925553] clk_core_prepare+0x3c/0x3b0 [ 62.929529] clk_prepare+0x2c/0x50 [ 62.932973] samsung_hdmi_phy_probe+0xc4/0x320 [ 62.937462] platform_probe+0x6c/0xe0 [ 62.941168] really_probe.part.0+0x9c/0x310 [ 62.945397] __driver_probe_device+0x98/0x144 [ 62.949799] driver_probe_device+0xc8/0x160 [ 62.954029] __device_attach_driver+0xbc/0x124 [ 62.958519] bus_for_each_drv+0x78/0xd0 [ 62.962397] __device_attach+0xd8/0x180 [ 62.966277] device_initial_probe+0x18/0x2c [ 62.970505] bus_probe_device+0xa0/0xac [ 62.974383] deferred_probe_work_func+0x88/0xc4 [ 62.978959] process_one_work+0x288/0x6d4 [ 62.983009] worker_thread+0x78/0x464 [ 62.986688] kthread+0x158/0x164 [ 62.989958] ret_from_fork+0x10/0x20 Signed-off-by:
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Dong Aisheng authored
PM domains on some SoCs (e.g. i.MX8MP) may depend on clocks to work properly. For such domains, PD clocks must be enabled first before powering up domain and then can be gated later when powering off. Usually PD drivers could implement it within genpd->power_on()/power_off(). However, there's a potential A-B/B-A deadlock between Clock and PM domain framework in current kernel. e.g. Possible unsafe locking scenario: CPU0 CPU1 ---- ---- genpd_power_on(genpd) lock(&genpd->mlock); clk_set_rate lock(prepare_lock); clk_pm_runtime_get() genpd_runtime_resume(genpd) lock(&genpd->mlock); clk_prepare() lock(prepare_lock); NOTE: assume CPU0 and CPU1 are accessing the same PD. For example in real life, clock controller and device using the same PD. This is a known issue in latest upstream kernel and still not get fixed. This patch abstracts this feature, implement it in PM domain core and moving the clock operations out of genpd_{lock|unlock} in order to address this potential A-B/B-A deadlock issue. A new flag GENPD_FLAG_PM_PD_CLK was introduced for driver to indicate the core to use it. Before fix, the locking sequence is A-B/B-A, potentially deadlock, after fix, the locking sequence changed to A-B/A-B. NOTE: this feature does not support clock controller using a sub-power domains which has a parent domains using PD clocks. There's lockdep warning, if enabled, about this user case. Signed-off-by:
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- May 21, 2022
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Adrian Alonso authored
Fix build warning [-Wstringop-overread] imx-pcm512x.c: In function ‘imx_pcm512x_probe’ imx-pcm512x.c:425:9: warning: ‘memcpy’ reading 600 bytes from a region of size 200 Fix: Match reserved number of dai_link with actual supported by imx-pcm512x sound machine driver. Signed-off-by:
Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by:
Shengjiu Wang <shengjiu.wang@nxp.com> (cherry picked from commit bdfd51a4) Acked-by:
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- May 18, 2022
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Joy Zou authored
The sdma memcpy test fail due to the channel priority not configured. The sdma_config_write-> sdma_config_channel-> sdma_set_channel_priority didn't be called in memcpy, So there are only memcpy test fail. The test fail log : root@imx8mnevk:~# echo 2000 > /sys/module/dmatest/parameters/timeout root@imx8mnevk:~# echo 1 > /sys/module/dmatest/parameters/iterations root@imx8mnevk:~# echo dma0chan1 > /sys/module/dmatest/parameters/channel [ 248.264090] dmatest: Added 1 threads using dma0chan1 root@imx8mnevk:~# echo 1 > /sys/module/dmatest/parameters/run [ 253.961791] dmatest: Started 1 threads using dma0chan1 root@imx8mnevk:~# [ 255.967043] dmatest: dma0chan1-copy0: result #1: 'test timed out' with src_off=0xc4 dst_off=0x3c len=0x3ec0 (0) [ 255.977236] dmatest: dma0chan1-copy0: summary 1 tests, 1 failures 0.49 iops 7 KB/s (0) This patch adds sdma_set_channel_priority for memcpy in transfer_init. Fixes: 11109759 ("MLK-25465-1 dmaengine: imx-sdma: move runtime behind to transfer phase") Signed-off-by:
Joy Zou <joy.zou@nxp.com> Reviewed by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by:
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Joy Zou authored
In order to call sdma_runtime_resume, the driver call pm_runtime_get_sync and pm_runtime_enable when the pm_runtime is false, it may be confused. The handler of true and false pm_runtime are mixed in sdma_remove function. This patch calls directly sdma_runtime_resume and remove pm_runtime_enable when the pm_runtime is false, and separate the handler of true and false pm_runtime. Signed-off-by:
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Joy Zou authored
If external firmware has not been loaded, the sdma driver should return as soon as possible for client using ram script. The original firmware load check in sdma_transfer_init, if firmware is not ready, the sdma_config_write also will run, it is unnecessary. This patch checks firmware load status earlier and return fail immediately in sdma_config_write if firmware not ready and use ram script. Signed-off-by:
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Joy Zou authored
The issue can be triggered with the sdma pm_runtime false. If the dma client try to use sdma in boot phase, it may cause system hang. The sdma driver really enable clk after sdma load firmware, the clk_disable_unused will disable the SDMA1_ROOT_CLK before the sdma driver enable clk. This issue will comes if access the sdma register when the SDMA1_ROOT_CLK is disable. This issue is very easy to reproduce with hdmi connected displayer on imx7d-sbd board which the i2c will use sdma early before sdma firmware loaded and clock enabled. The client i2c calls dmaengine_prep_slave_single->device_prep_slave_sg ->sdma_prep_slave_sg->sdma_config_write->sdma_config_channel to get descriptor in boot phase. Then, the function sdma_config_channel will access sdma registers. If clk is disable will cause system hang. This patch adds clk_enable and clk_disable to make sure the clk enable before access sdma hardware. Signed-off-by:
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Joy Zou authored
The issue can be triggered with the sdma pm_runtime true. The dma clinet pcm calls snd_dmaengine_pcm_trigger->device_prep_dma_cyclic ->sdma_prep_dma_cyclic->pm_runtime_get_sync->sdma_transfer_init ->sdma_load_context to get descriptor. The sdma_buffer_descriptor bd0 is allocated by sdma_runtime_resume. The sdma_runtime_resume function will not be called because the runtime_status is RPM_ACTIVE. The sdma_load_context accessing bd0 will cause dump. The fail log as follow: [ 13.613406] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 [ 13.622200] Mem abort info: [ 13.625010] ESR = 0x96000044 [ 13.628078] EC = 0x25: DABT (current EL), IL = 32 bits [ 13.633402] SET = 0, FnV = 0 [ 13.636469] EA = 0, S1PTW = 0 [ 13.639620] Data abort info: [ 13.642515] ISV = 0, ISS = 0x00000044 [ 13.646364] CM = 0, WnR = 1 [ 13.649347] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000105ac5000 [ 13.655800] [0000000000000000] pgd=0000000000000000, p4d=0000000000000000 [ 13.662605] Internal error: Oops: 96000044 [#1] PREEMPT SMP [ 13.668186] Modules linked in: [ 13.671259] CPU: 3 PID: 695 Comm: alsa-sink-30c20 Not tainted 5.10.72-00003-g5f44cf7c854d-dirty #14 [ 13.680315] Hardware name: NXP i.MX8MPlus EVK board (DT) [ 13.685646] pstate: 80000085 (Nzcv daIf -PAN -UAO -TCO BTYPE=--) [ 13.691671] pc : sdma_transfer_init+0x21c/0x26c [ 13.696223] lr : sdma_transfer_init+0x1bc/0x26c [ 13.700767] sp : ffff800012d9bb80 [ 13.704095] x29: ffff800012d9bb80 x28: 0000000000000003 [ 13.709425] x27: ffff0000c19c46a8 x26: 0000000000000000 [ 13.714754] x25: 0000000000000080 x24: ffff0000c19c0080 [ 13.720083] x23: 00000000000003c2 x22: 0000000000000020 [ 13.725412] x21: ffff800011f4d200 x20: ffff0000d499a900 [ 13.730741] x19: ffff0000c19c0298 x18: ffffffffffffffff [ 13.736069] x17: 0000000000000000 x16: 0000000000000000 [ 13.741398] x15: ffff800092d9b7e7 x14: 3030303165303320 [ 13.746726] x13: ffff800011b517b0 x12: 0000000000001000 [ 13.752055] x11: 000000000000037f x10: ffff800011b517b0 [ 13.757384] x9 : 0000000000000000 x8 : ffff800011f4d280 [ 13.762712] x7 : 0000000000000000 x6 : 000000000000003f [ 13.768041] x5 : 0000000000000040 x4 : 0000000000000000 [ 13.773369] x3 : 0000000000000004 x2 : 0000000000000000 [ 13.778697] x1 : 0000000000000000 x0 : 0000000001830020 [ 13.784025] Call trace: [ 13.786493] sdma_transfer_init+0x21c/0x26c [ 13.790696] sdma_prep_dma_cyclic+0x88/0x2e4 [ 13.794984] snd_dmaengine_pcm_trigger+0xec/0x1c0 [ 13.799706] dmaengine_pcm_trigger+0x18/0x24 [ 13.803995] snd_soc_pcm_component_trigger+0x48/0xf0 [ 13.808977] soc_pcm_trigger+0xa8/0xd0 [ 13.812744] snd_pcm_do_start+0x38/0x44 [ 13.816597] snd_pcm_action_single+0x48/0xac [ 13.820885] snd_pcm_action+0x7c/0x9c [ 13.824566] snd_pcm_action_lock_irq+0x8c/0xbc [ 13.829026] snd_pcm_common_ioctl+0xfa4/0x11c0 [ 13.833487] snd_pcm_ioctl+0x34/0x50 [ 13.837083] __arm64_sys_ioctl+0xa8/0xf0 [ 13.841024] el0_svc_common.constprop.0+0x78/0x1c4 [ 13.845829] do_el0_svc+0x28/0x9c [ 13.849163] el0_svc+0x14/0x20 [ 13.852235] el0_sync_handler+0xa4/0x130 [ 13.856174] el0_sync+0x180/0x1c0 [ 13.859507] Code: b90026a0 52800400 531b6ad6 72a03060 (b9000340) [ 13.865605] ---[ end trace 0f90c4454359a810 ]--- [ 13.870233] note: alsa-sink-30c20[695] exited with preempt_count 2 This patch removes pm_runtime_set_active in sdma_probe. The clk is disable and the power is on when sdma probe, but the genpd_dev_pm_sync will sync power. So we think the runtime_status is RPM_SUSPENDED. The default runtime_status is RPM_SUSPENDED. This patch adds pm_runtime_set_suspended in order to improve code readability. The sdma_runtime_resume will be called. This issue is very hard to reproduce with yocto rootfs. If it uses auto login with ubuntu rootfs which is more easy to reproduce on kernel 5.10, but not easy on kernel 5.15. Reviewed-by:
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Joy Zou authored
If there is more than one sdma controller, the first controller load sdma firmware using fallback failed in first time, it will retry load sdma firmware again. But the second sdma controller error state clean up may be still not finished (the firmware request priv data has not been released). So the retry will fail immediately due to get the old firmware priv data. The fail log as follow: [ 62.505753] imx-sdma 30e10000.dma-controller: external firmware not found, using ROM firmware [ 62.599868] imx-sdma 30bd0000.dma-controller: firmware found. [ 62.605808] imx-sdma 30bd0000.dma-controller: loaded firmware 4.6 This patch adds a bit delay to wait for the second controller firmware priv data released. This issue is very hard to reproduce with yocto rootfs. The 20ms delay is tested value with ubuntu rootfs which is more easy to reproduce. Signed-off-by:
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- May 10, 2022
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Willem de Bruijn authored
[ Upstream commit ec6af094 ] Packet sockets may switch ring versions. Avoid misinterpreting state between versions, whose fields share a union. rx_owner_map is only allocated with a packet ring (pg_vec) and both are swapped together. If pg_vec is NULL, meaning no packet ring was allocated, then neither was rx_owner_map. And the field may be old state from a tpacket_v3. Fixes: 61fad681 ("net/packet: tpacket_rcv: avoid a producer race condition") Reported-by:
Syzbot <syzbot+1ac0994a0a0c55151121@syzkaller.appspotmail.com> Signed-off-by:
Willem de Bruijn <willemb@google.com> Reviewed-by:
Eric Dumazet <edumazet@google.com> Link: https://lore.kernel.org/r/20211215143937.106178-1-willemdebruijn.kernel@gmail.com Signed-off-by:
Jakub Kicinski <kuba@kernel.org> Signed-off-by:
Sasha Levin <sashal@kernel.org> (cherry picked from commit feb116a0)
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- May 09, 2022
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Haibo Chen authored
For gpio controller contain register PDDR, when set one target bit, current logic will clear all other bits, this is wrong. Use operator '|=' to fix it. Reviewed-by:
Clark Wang <xiaoning.wang@nxp.com> Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
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- Apr 15, 2022
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Abel Vesa authored
ADC1 has its own clock, so add it. Signed-off-by:Abel Vesa <abel.vesa@nxp.com>
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Frank Li authored
ADC1 is not defined in pd driver on 8QM. Signed-off-by:
Frank Li <Frank.Li@nxp.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- Jan 26, 2022
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Robert Chiras authored
Add support for frame format update using the atomic_update call. Android, for example, changes the frame format after the atomic_enable call, so without this, the colors are not right. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com> Reviewed-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com> Tested-by:
Bo Zhang <bo.zhang@nxp.com> [ Liu Ying: Fix the way to get old plane state in primay's ->atomic_update() ] Signed-off-by:
Liu Ying <victor.liu@nxp.com> (cherry picked from commit 278d9757) Signed-off-by:
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- Jan 17, 2022
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Laurentiu Palcu authored
The cause for the DPU1 missing interrupts, sometimes, during bootup is the CHn-MASK13 register of the IRQ STEER module being 0x0. Which means: all interrupts are masked. This situation happens because the sequence we unmask/mask the interrupts in dpu_irq_init()/dpu_irq_exit() is wrong. Currrently, we do it like this: dpu_irq_init(): irq_set_chained_handler_and_data() -> unmasks irq (writel to CHn-MASK) irq_chip_pm_get() -> calls IRQ steer resume() synchronously dpu_irq_exit(): irq_chip_pm_put() -> calls IRQ steer suspend() asynchronously irq_set_chained_handler_and_data() -> masks irq (writel to CHn-MASK) The first time dpu_irq_exit() is called is because dpu-core probe fails. However, since the irq_chip_pm_put() is asynchronous, it means that irq_set_chained_handler_and_data() will be called immediately to mask the interrupts. Here, it's a matter of luck if the IRQ steer suspend is called before or after we mask the interrupts. But, when the problem happens, the IRQ steer suspend is called after and the registers are saved in the masked state (ie. all 0x0). The second time dpu-core is probed, the dpu_irq_init() is called and the interrupts unmasked first, then irq_chip_pm_get() is called synchronously, which in turn calls IRQ steer resume and the registers are restored from the saved state (ie. registers in masked state: 0x0). Hence, we end up with the wrong value in the CHn-MASK registers. The fix for this is simple: reverse the order we call irq_chip_pm_get/irq_chip_pm_put and irq_set_chained_handler_and_data. Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@oss.nxp.com> Reviewed-by:
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- Dec 18, 2021
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Han Xu authored
When enabling the OCTAL DTR read on DXL platform, to fix the UBIFS mount issue, the driver handles the OCTAL DTR read with odd address by reading one more byte and discard the first byte, but it involved some issues that can be triggered by mtd stress test, which may read from random start address with random length. First issue is reading data from odd address and data length is larger than rxfifo. nxp_fspi_adjust_op_size() sets the data size align to rxfifo size, but is over the rxfifo size if reads one more byte and causes controller timeout. Second issue happens when memcpy from src to dst in odd address cases. The fist byte from src discarded, the pointer to src should move N bytes forward and dst pointer moves N-1 bytes. Previous implementation reads one more byte, even there is nothing in FIFO, which triggers the WARN_ON() in driver. This change handles the OCTAL DTR with odd address before normal rxfifo read. nxp_fspi_adjust_op_size() changes the data size to an odd number so this special case only happens once when reading large chunk of data. Signed-off-by:
Han Xu <han.xu@nxp.com> Reviewed-and-Tested-by:
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- Dec 08, 2021
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Ye Li authored
Current driver may meet reconfigure failure caused by below reasons: 1. The wdog on iMX7ULP has different behavior after RCS valid. It needs to wait more than 2.5 wdog clock for clock sync before next reconfiguration, while imx8ulp wdog does not need such delay. 2. After unlock, there is 128 bus clock window opened for reconfiguration, but on iMX8ULP, the HW can't guarantee the latency. So it is possible the window is closed before the writing arrives to wdog. 3. If the PRES is enabled, the RCS valid time becomes x256 to the time of PRES disabled. It is about 1715ms on iMX8ULP. So We have to increase the RCS timeout and can't wait it in IRQ disabled. The patch updates the driver to handle failures 1. Using different wait for unlock and RCS. Unlock valid time is very short and only related to bus clock. It must be in IRQ disabled to avoid being interrupted in 128 clock window. But for RCS time, it is longer and ok for IRQ enabled. 2. Add retry for any reconfigure failure with default 5 times. 3. Add "fsl,imx8ulp-wdt" compatile string for iMX8ULP and afterwards platform which don't need more 2.5 wdog clock after RCS valid. For imx7ulp, add post delay of 2.5 clock after RCS valid. Signed-off-by:
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Frank Li authored
This issue was found at android12 MTP. 1. MTP submit many out urb request. 2. Cancel left requests (>20) when enough data get from host 3. Send ACK by IN endpoint. 4. MTP submit new out urb request. 5. 4's urb never complete. TRACE LOG: MtpServer-2157 [000] d..3 1287.150391: cdns3_ep_dequeue: ep1out: req: 00000000299e6836, req buff 000000009df42287, length: 0/16384 zsi, status: -115, trb: [start:87, end:87: virt addr 0x80004000ffd50420], flags:1 SID: 0 MtpServer-2157 [000] d..3 1287.150410: cdns3_gadget_giveback: ep1out: req: 00000000299e6836, req buff 000000009df42287, length: 0/16384 zsi, status: -104, trb: [start:87, end:87: virt addr 0x80004000ffd50420], flags:0 SID: 0 MtpServer-2157 [000] d..3 1287.150433: cdns3_ep_dequeue: ep1out: req: 0000000080b7bde6, req buff 000000009ed5c556, length: 0/16384 zsi, status: -115, trb: [start:88, end:88: virt addr 0x80004000ffd5042c], flags:1 SID: 0 MtpServer-2157 [000] d..3 1287.150446: cdns3_gadget_giveback: ep1out: req: 0000000080b7bde6, req buff 000000009ed5c556, length: 0/16384 zsi, status: -104, trb: [start:88, end:88: virt addr 0x80004000ffd5042c], flags:0 SID: 0 .... MtpServer-2157 [000] d..1 1293.630410: cdns3_alloc_request: ep1out: req: 00000000afbccb7d, req buff 0000000000000000, length: 0/0 zsi, status: 0, trb: [start:0, end:0: virt addr (null)], flags:0 SID: 0 MtpServer-2157 [000] d..2 1293.630421: cdns3_ep_queue: ep1out: req: 00000000afbccb7d, req buff 00000000871caf90, length: 0/512 zsi, status: -115, trb: [start:0, end:0: virt addr (null)], flags:0 SID: 0 MtpServer-2157 [000] d..2 1293.630445: cdns3_wa1: WA1: ep1out set guard MtpServer-2157 [000] d..2 1293.630450: cdns3_wa1: WA1: ep1out restore cycle bit MtpServer-2157 [000] d..2 1293.630453: cdns3_prepare_trb: ep1out: trb 000000007317b3ee, dma buf: 0xffd5bc00, size: 512, burst: 128 ctrl: 0x00000424 (C=0, T=0, ISP, IOC, Normal) SID:0 LAST_SID:0 MtpServer-2157 [000] d..2 1293.630460: cdns3_doorbell_epx: ep1out, ep_trbaddr ffd50414 .... irq/241-5b13000-2154 [000] d..1 1293.680849: cdns3_epx_irq: IRQ for ep1out: 01000408 ISP , ep_traddr: ffd508ac ep_last_sid: 00000000 use_streams: 0 irq/241-5b13000-2154 [000] d..1 1293.680858: cdns3_complete_trb: ep1out: trb 0000000021a11b54, dma buf: 0xffd50420, size: 16384, burst: 128 ctrl: 0x00001810 (C=0, T=0, CHAIN, LINK) SID:0 LAST_SID:0 irq/241-5b13000-2154 [000] d..1 1293.680865: cdns3_request_handled: Req: 00000000afbccb7d not handled, DMA pos: 185, ep deq: 88, ep enq: 185, start trb: 184, end trb: 184 Actually DMA pos already bigger than previous submit request afbccb7d's TRB (184-184). The reason of (not handled) is that deq position is wrong. The TRB link is below when irq happen. DEQ LINK LINK LINK LINK LINK .... TRB(afbccb7d):START DMA(EP_TRADDR). Original code check LINK TRB, but DEQ just move one step. LINK DEQ LINK LINK LINK LINK .... TRB(afbccb7d):START DMA(EP_TRADDR). This patch skip all LINK TRB and sync DEQ to trb's start. LINK LINK LINK LINK LINK .... DEQ = TRB(afbccb7d):START DMA(EP_TRADDR). Acked-by:
Peter Chen <peter.chen@kernel.org> Cc: stable <stable@vger.kernel.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- Nov 23, 2021
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Jacky Bai authored
The clock will be get failed if the clock name is not 'snvs', it is not what we expected if the clock need to be managed by driver. As for the SNVS module, there is only one clock for it, so assigned a unspecified clock name 'NULL'. Signed-off-by:
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Jacky Bai authored
The SNVS moudule is not used only by the linux, it may also used by other SW component is secure world. No sense to gate it by linux, so mark it as critical clock. Signed-off-by:
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Robin Gong authored
Fix Coverity Issue:17611886 Uninitialized scalar variable, though DEV_TO_DEV case never care residue of current transfer by calling dmaengine_tx_status. Signed-off-by:
Robin Gong <yibin.gong@nxp.com> Reviewed-by:
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- Nov 12, 2021
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Peng Fan authored
Correct clk settings for usdhc/mipi/dsp in ND mode In ND mode -not able to configure IMX8ULP_CLK_SPLL3_PFD2 to 396M, so change to use IMX8ULP_CLK_SPLL3_PFD2_DIV1 and clk set to 198M. - Update HIFI_SEL to source from PLL4_PFD0 and set clk to 260M according to STA - Decrease mipi_csi node clk pll4_pfd1 to 396M With this patch, there is no clk failed to set rate or reparent failure for the devices. Reviewed-by:
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- Nov 08, 2021
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Ye Li authored
According to measure on i.MX7ULP and i.MX8ULP, the RCS done needs about 3400us and 6700us respectively. So current 20us timeout is not enough. When reconfiguring is on-going, unlock and configure CS will lead to unknown result. Increase the wait timeout value to 10ms and check the return value of RCS wait to fix the issue Signed-off-by:
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Ye Li authored
When bootloader has enabled the CMD32EN bit, switch to use 32bits unlock command to unlock the CS register. Using 32bits command will help on avoiding 16 bus cycle window violation for two 16 bits commands. Signed-off-by:
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- Nov 05, 2021
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Fabio Estevam authored
Booting with imx8mq-evk-lcdif-rm67191.dtb and running a simple: ifconfig eth0 down causes the RM67191 OLED display to show only garbage. Fix this issue by requesting bus_freq to operate at the maximum frequency, which avoids the DDR clock frequency to get lowered and corrupt the framebuffer. Reported-by:
Renato Frias <renato.frias@nxp.com> Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Chancel Liu authored
The buffer size of rpmsg-micfil pcm is modified incorrectly in previous code. This patch fixes the bug. Fixes: d1b8e2b7 ("MLK-25741-5: ASoC: fsl_rpmsg: Support rpmsg-micfil") Reviewed-by:
Chancel Liu <chancel.liu@nxp.com> Acked-by:
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- Nov 04, 2021
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Robert Chiras authored
This flag was automatically used in the DSI driver, making this panel work, but the way that flag was used was wrong. Since, fixing the use of this flag in the DSI driver now breaks this panel, just add it here. Signed-off-by:
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Robert Chiras authored
In order to respect the DSI protocol, make sure that the auto-insert EOTP is enabled with regard to the EOT_PACKET flag, not with regard of the NON_CONTINUOUS clock flag. Signed-off-by:
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- Nov 03, 2021
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Sandor Yu authored
CDNS HDCP driver is selected when iMX8 CDNS platform driver enabled. Remove it from imx_v8_defconfig. Signed-off-by:
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Sandor Yu authored
DRM_CDNS_HDMI_HDCP has been renamed to DRM_CDNS_HDCP in folder drivers/gpu/drm/bridge/cadence update it to avoid build error. Signed-off-by:
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