KVM: x86/pmu: Fix and isolate TSX-specific performance event logic

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2074832



commit e644896f
Author: Like Xu <likexu@tencent.com>
Date:   Wed Mar 9 16:42:57 2022 +0800

    KVM: x86/pmu: Fix and isolate TSX-specific performance event logic

    HSW_IN_TX* bits are used in generic code which are not supported on
    AMD. Worse, these bits overlap with AMD EventSelect[11:8] and hence
    using HSW_IN_TX* bits unconditionally in generic code is resulting in
    unintentional pmu behavior on AMD. For example, if EventSelect[11:8]
    is 0x2, pmc_reprogram_counter() wrongly assumes that
    HSW_IN_TX_CHECKPOINTED is set and thus forces sampling period to be 0.

    Also per the SDM, both bits 32 and 33 "may only be set if the processor
    supports HLE or RTM" and for "IN_TXCP (bit 33): this bit may only be set
    for IA32_PERFEVTSEL2."

    Opportunistically eliminate code redundancy, because if the HSW_IN_TX*
    bit is set in pmc->eventsel, it is already set in attr.config.

Reported-by: Ravi Bangoria <ravi.bangoria@amd.com>
Reported-by: Jim Mattson <jmattson@google.com>
    Fixes: 103af0a9 ("perf, kvm: Support the in_tx/in_tx_cp modifiers in KVM arch perfmon emulation v5")
Co-developed-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Like Xu <likexu@tencent.com>
    Message-Id: <20220309084257.88931-1-likexu@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>