drm/i915/dg2: Add Wa_16013000631

Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.

v2:
 - Move pipe control from xcs indirect context to the rcs indirect
   context.  We'll eventually need this on the CCS engines too, but
   support for those hasn't landed yet.

Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-5-matthew.d.roper@intel.com