Add nrf52832 spi driver compatibility with FW1.0 and FW2.0.
1.Add KXR_SPI_WORK_MODE_OLD mode support for FW1.0.
2.Add jsmem node support for FW1.0.
3.Fix bind right controller failed.
4.Fix send vibration failed.

CRs-Fixed: 3672431
Change-Id: I06407f987b47778290fe224ee9795c89e5c931d1
Signed-off-by: Zhao Zha <quic_zhaozha@quicinc.com>

adding missing NULL check for qcedev_areq in
qcedev_offload_cipher_req_cb and qcedev_cipher_req_cb.

Change-Id: Ibbb037b12b1c6264376fe1f3185bd0b392447a65
Signed-off-by: Udit Tiwari <quic_utiwari@quicinc.com>

Change-Id: Id5e4d9e09914157ccd9cc3b052a03114ddc6cf85

This reverts commit 18851a16.

Change-Id: I4710cdea1a2be15bb45012dcbbe009117210df89
Signed-off-by: Pawan Chilka <quic_pchilka@quicinc.com>

If sharedmem cannot be unmapped from the mmu, it can still be accessed
by the GPU. Therefore it is not safe to free the backing memory. In the
case that unmap fails, do not free it or return it to the system.

Change-Id: Iad3e86d043f129a4d71cf862865d9033d4a315e3
Signed-off-by: Lynus Vaz <quic_lvaz@quicinc.com>

Spinlock in current scenario can be interrupted thus during ongoing
ISR. If callback received from dsp, attempt to acquire same lock
again will result into recursive spinlock with wait on queue to
acquire lock again. Modify spinlocks with global variable gfa to
non interruptible spinlocks in order to avoid this scenario.

Change-Id: I5ae4864370d94ae0e0e19d3d4939ada41d609234
Signed-off-by: Abhinav Parihar <quic_parihar@quicinc.com>

The netlink policy NLA_UNSPEC is no longer
accepted.

Fix this by assigning appropriate nla policy
for the attributes used in the vendor subcommand.

Change-Id: I9e8aa0de26d627eff555de65a0b47159eed6217b
Signed-off-by: Subrat Dash <quic_sdash@quicinc.com>

Add support in the driver to manage power without enabling pm runtime.
UART driver gives control to user space client to vote for clock on/off
by exposing ioctls. These vote clock on/off APIs depend on PM runtime
framework for power related operations.

This change relaxes driver from depending on userspace ioctls to invoke
runtime resume/suspend for basic uart functionality which will now be
done by system suspend/resume. This will block PM framework API's and
use system suspend/resume API for UART on/off.

Change-Id: Idf0632c0e2d40907f7a226cd7e3e814d1c1f6751
Signed-off-by: Ashish Kori <akori@codeaurora.org>
Signed-off-by: Prasanna S <quic_prass@quicinc.com>

Add framework for piggy back of mo at time of callback too.
cherrypick-hash 3eda31424a62866a369f2d7b7c5336b2fe96a4e4.

Change-Id: I79e20ca4e2b32f17d4baa97195993428e3cc8f7b
Signed-off-by: Divisha Bisht <quic_divibish@quicinc.com>

The VBO bind operation is often synchronous, and needs to be waited
on by the ioctl thread. Allocate the completion struct used to synchronize
between the ioctl and bind operation on the heap for simplicity.

Change-Id: I709d417dbd3fb0ecd1150439f598fc3629de478e
Signed-off-by: Lynus Vaz <quic_lvaz@quicinc.com>

Enable access protection for LPAC pipeline so that command
processor will restrict access to a block of registers from
within the command stream. Any attempt to access protected
register space will result in fault.

Change-Id: Ia8d391f7b9ad1b5d38e7d4d8ac727d2d3f54f53a
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
Signed-off-by: Sanjay Yadav <quic_sanjyada@quicinc.com>

This reverts commit ee97ee45.

Reason for revert: not adapt FW1.0.

Change-Id: If4de56a61f68fa15652d08211a7ff2f41a939561
Signed-off-by: Zhao Zha <quic_zhaozha@quicinc.com>

As per PCIE phy HDR all the clocks are parked low before parking
the phy in low power down mode.

As we need ahb clk enabled to access registers disable all clocks
except ahb clock and do the phy configurations and then disable
ahb clock in suspend path and do vice versa in resume path.

Change-Id: I4710cdea1a2be15bb45012dcbbe009117210d7f8
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
Signed-off-by: Pawan Chilka <quic_pchilka@quicinc.com>

Removed secure registers from the dumps to avoid
access issues. Added RO registers instead of secure
registers.

Change-Id: Ie6ef5a93b26a57572eeaae74887357f6aa55870e
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>

SDPM driver probing is failed if any of the clocks configured in
devicetree is not available. Update sdpm driver probe logic to
proceed with the available clocks.

Change-Id: I8e66fb9028fa3f2f4f1b45bf9c2cc16e7e6950a9
Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com>

There can be cases where logical to physical CPUs may not be 1:1
mapping. Use physical CPU IDs instead of logical to read/write
LLCC PMU registers.

Change-Id: I2fe549826bdbfa33055d176b2763617a6b775986
Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>

1.Fix lock issues of Adapt to FW1.0.
2.Fix no ack issue when updated  FW2.0.

CRs-Fixed: 3666209
Change-Id: I800a187ca69030b5326be0c19bdf8094f3973d26
Signed-off-by: Zhao Zha <quic_zhaozha@quicinc.com>

Add wmi ARC (adaptive rate control) interface
for config command, response, and event.

The asynchronous ARC notification from firmware are sent to
user space through netlink events.

Change-Id: I22e351e4b146fa4393f57f2bdd2deaedb5d149ce
Signed-off-by: Subrat Dash <quic_sdash@quicinc.com>

Change-Id: I581b19754e822e0d852018fdb59cee6d61054d73

Raw commands are designed to be used during boot up only. Register
a global context (managed by KGSL) with GMU to submit perfcounter
select PM4 packets for SP/TP/VFD blocks.

Change-Id: Ie6cb8ac5325d323b1e9a48ce8e22af0f019fa1eb
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>

Optimize data transmission,adapt to FW2.0.
1.Add SPI to upgrade HMD FW.
2.Add HMD nordic upgrade controller.
3.Optimize data transmission,kernel mapping pass data to HAL.

CRs-Fixed: 3639549
Change-Id: I04c587d628277ab26fde536f506e32a1f9c703ca
Signed-off-by: Wei Tan <quic_weitan@quicinc.com>

We are seeing M_TX_FIFO_WATERMARK_EN timeout during
console_write and M_CMD_OVERRUN is getting set which
indicates a new command is initialized by SW, before
the previous one has been completed. There is some data
in TX FIFO and before UART transaction is finished,
console_write() is called again without clearing the
m_irq_status.

During the next console_write if tx geni is
active and previous console_write was incomplete,
ensure the m_irq_status is cleared by calling
msm_geni_serial_poll_tx_done before triggering further
write operations.

Change-Id: I440f8d1e5234b2d9bb66b41ed1532bfec0088ce2
Signed-off-by: Prasanna S <quic_prass@quicinc.com>

We are seeing M_TX_FIFO_WATERMARK_EN timeout during
console_write and M_CMD_OVERRUN is getting set which
indicates a new command is initialized by SW, before
the previous one has been completed. There is some data
in TX FIFO and before UART transaction is finished,
console_write() is called again without clearing the
m_irq_status.

During the next console_write if tx geni is
active and previous console_write was incomplete,
ensure the m_irq_status is cleared by calling
msm_geni_serial_poll_tx_done before triggering further
write operations.

Change-Id: I440f8d1e5234b2d9bb66b41ed1532bfec0088ce2
Signed-off-by: Prasanna S <quic_prass@quicinc.com>

Change-Id: I3b12a27aa59a780d74129d0401b049bb2677d0a2