- Sep 28, 2023
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Caleb Connolly authoredThis module causes usb devices to be reconnected when it probes, this breaks usb boot... Signed-off-by:
Caleb Connolly <caleb.connolly@linaro.org> -
Caleb Connolly authored
Signed-off-by:Caleb Connolly <caleb.connolly@linaro.org>
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- Sep 27, 2023
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Caleb Connolly authored
Signed-off-by:Caleb Connolly <caleb.connolly@linaro.org>
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- Aug 01, 2023
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Dmitry Baryshkov authoredSigned-off-by:Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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- Jul 28, 2023
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Enable the remote processors and tighten up the regulators to enable Wi-Fi (and possibly GPS, untested) functionality on the RB2. Signed-off-by:Konrad Dybcio <konrad.dybcio@linaro.org>
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Enable the aDSP and cDSP remoteproc nodes on Qualcomm QRB4210 RB2 board. Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230516075908.2323372-4-bhupesh.sharma@linaro.org
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Enable the A610 GPU and provide a firmware path to the ZAP blob. Signed-off-by:
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Introduce nodes for the A610 GPU and its GMU wrapper along with the speedbin fuse entry in QFPROM. Reviewed-by:
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A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by:
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A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Reviewed-by:
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Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by:
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The GPU can only be one at a time. Turn a series of ifs into if + elseifs to save some CPU cycles. Reviewed-by:
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Adreno 619 expects some tunables to be set differently. Make up for it. Fixes: b7616b5c ("drm/msm/adreno: Add A619 support") Reviewed-by:
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A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by:
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A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: -
A610 and A619_holi don't support the feature. Disable it to make the GPU stop crashing after almost each and every submission - the received data on the GPU end was simply incomplete in garbled, resulting in almost nothing being executed properly. Extend the disablement to adreno_has_gmu_wrapper, as none of the GMU wrapper Adrenos that don't support yet seem to feature it. Reviewed-by:
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Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by: -
Since the introduction of A6xx support, we've been enabling the CX GMU power counter 0 in a bit of a weird spot. Move it to hw_init so that GMU wrapper GPUs can reuse the same code paths. As a bonus, this order makes it easier to compare mainline and downstream register access traces. Signed-off-by: -
Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by:
Rob Clark <robdclark@gmail.com> Reviewed-by:
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Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. This is typically done automatically on successful GX collapse, but in case that fails, we should take care of it. Also, add a memory barrier to ensure it's gone through before jumping to further initialization. Reviewed-by:
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Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper GPUs and reuse it in a6xx_gmu_force_off(). This helper, contrary to the original usage in GMU code paths, adds a readback+delay sequence to ensure that the reset is never deasserted too quickly due to e.g. OoO execution going crazy. Signed-off-by: -
Unify the indentation and explain the cryptic 0xF value. Reviewed-by:
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This function is responsible for telling the GPU to halt transactions on all of its relevant buses, drain them and leave them in a predictable state, so that the GPU can be e.g. reset cleanly. Move the function to a6xx_gpu.c, remove the static keyword and add a prototype in a6xx_gpu.h to accomodate for the move. Reviewed-by:
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As pointed out by Akhil during the review process of GMU wrapper introduction [1], it makes sense to move this write into the function that's responsible for forcibly shutting the GMU off. It is also very convenient to move this to GMU-specific code, so that it does not have to be guarded by an if-condition to avoid calling it on GMU wrapper targets. Move the write to the aforementioned a6xx_gmu_force_off() to achieve that. No effective functional change. [1] https://lore.kernel.org/linux-arm-msm/20230501194022.GA18382@akhilpo-linux.qualcomm.com/ Reviewed-by:
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These two will be reused by at least A619_holi in the non-gmu paths. Turn them non-static them to make it possible. Reviewed-by:
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The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Dmitry Baryshkov authored
This reverts commit 87cb554b, it is a duplicate of 45283bb2.
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- Jul 27, 2023
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Add interconnect provider nodes and hook up interconnects to consumer devices, including bwmon. Signed-off-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
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Vladimir Zapolskiy authored
This reverts commit 3e07da7b. The change is to be replaced by an updated version. Signed-off-by:
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- Jul 19, 2023
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Dmitry Baryshkov authored
Enable interconnects driver for SM6115, used on Qualcomm RB2 platform. Reported-by:
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Signed-off-by: -
Dmitry Baryshkov authored
Fix the voltages min/max properties in the DT regulators so that the voltage constraints are programmed correctly. They are regulator-min/max-microvolt, not -microvolts. Fixes: b4fe47d1 ("arm64: dts: qcom: qrb2210-rb1: Add regulators") Signed-off-by:
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Dmitry Baryshkov authored
For some reason cluster idle state causes the board to hang after boot. Disable it to make it work properly. Signed-off-by: -
Dmitry Baryshkov authored
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Following the BSP, disable the RETAIN_MEM and RETAIN_PERIPH bits on gcc_gpu_memnoc_gfx_clk. Signed-off-by:
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Following the BSP, disable the RETAIN_MEM and RETAIN_PERIPH bits on gcc_gpu_memnoc_gfx_clk. Signed-off-by:
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Enable the PMIC GPIO- and RESIN-connected buttons on the board. Signed-off-by:
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Enable the USB controller and HS/SS PHYs on qrb4210-rb2 board. Reviewed-by:
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Enable the Microchip mcp2518fd hosted on the SPI5 bus. Signed-off-by:
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