vfe-480 is copied from vfe-17x and has the same racy idle timeout bug as in
17x.

Fix the vfe_disable_output() logic to no longer be racy and to conform
to the 17x way of quiescing and then resetting the VFE.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

There are two problems with the current vfe_disable_output() routine.

Firstly we rightly use a spinlock to protect output->gen2.active_num
everywhere except for in the IDLE timeout path of vfe_disable_output().
Even if that is not racy "in practice" somehow it is by happenstance not
by design.

Secondly we do not get consistent behaviour from this routine. On
sc8280xp 50% of the time I get "VFE idle timeout - resetting". In this
case the subsequent capture will succeed. The other 50% of the time, we
don't hit the idle timeout, never do the VFE reset and subsequent
captures stall indefinitely.

Rewrite the vfe_disable_output() routine to

- Quiesce write masters with vfe_wm_stop()
- Set active_num = 0

remembering to hold the spinlock when we do so followed by

- Reset the VFE

Testing on sc8280xp and sdm845 shows this to be a valid fix.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Andrey Konovalov authored 1 year ago and Bryan O'Donoghue committed 1 year ago

In the current driver csid Test Pattern Generator (TPG) doesn't work.
This change:
- fixes writing frame width and height values into CSID_TPG_DT_n_CFG_0
- fixes the shift by one between test_pattern control value and the
  actual pattern.
So that TPG starts working, but with the below limitations:
- only test_pattern=9 works as it should
- test_pattern=8 and test_pattern=7 produce black frame (all zeroes)
- the rest of test_pattern's don't work (yavta doesn't get the data)
- regardless of the CFA pattern set by 'media-ctl -V' the actual pixel
  order is always the same (RGGB for any RAW8 or RAW10P format in
  4608x2592 resolution).

Tested with:

RAW10P format, VC0:
 media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4608x2592 field:none]'
 media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4608x2592 field:none]'
 media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
 v4l2-ctl -d /dev/v4l-subdev6 -c test_pattern=9
 yavta -B capture-mplane --capture=3 -n 3 -f SRGGB10P -s 4608x2592 /dev/video0

RAW10P format, VC1:
 media-ctl -V '"msm_csid0":2[fmt:SRGGB10/4608x2592 field:none]'
 media-ctl -V '"msm_vfe0_rdi1":0[fmt:SRGGB10/4608x2592 field:none]'
 media-ctl -l '"msm_csid0":2->"msm_vfe0_rdi1":0[1]'
 v4l2-ctl -d /dev/v4l-subdev6 -c test_pattern=9
 yavta -B capture-mplane --capture=3 -n 3 -f SRGGB10P -s 4608x2592 /dev/video1

RAW8 format, VC0:
 media-ctl --reset
 media-ctl -V '"msm_csid0":0[fmt:SRGGB8/4608x2592 field:none]'
 media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB8/4608x2592 field:none]'
 media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
 yavta -B capture-mplane --capture=3 -n 3 -f SRGGB8 -s 4608x2592 /dev/video0

[bod: Dropped changing test VC from 0xa to 0x0 fixes test patterns < 7 ]
Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

The 7251 sensor is a black and white Y10P sensor capable of delivering
640x480 @ 90 fps.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This reverts commit 463a75b31fec4c339d9e6a5d0214a079ee790400.

The 9734 is at i2c address 0x60 located on pins
cci_i2c_sda2/cci_i2c_scl2 denoted as cci1_i2c0. MCLK4 is used to clock
the chip with vreg_l3q, vreg_l5q and vreg_l1q providing dovdd, avdd and
dvdd respectively.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

The data sheet calls the input clock signal XVCLK not MCLK.
Change all upper and lower case instances of MCLK to XVCLK to align with
the data-sheet and associated PCBs.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Switch on the defconfig for the IR sensor.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

VC_MODE = 0 implies a two bit VC address.
VC_MODE = 1 is required for VCs with a larger address than two bits.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add in the ability to export registers of interest read-only via debugfs
for the VFE-17X block.

We can extend this out to other VFE versions later.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add in the ability to export registers of interest read-only via debugfs
for the CSIPHY 3ph block.

We can extend this out to other CSIPHY versions later.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add in the ability to export registers of interest read-only via debugfs
for the CSID-Gen2 block.

We can extend this out to other CSID versions later.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add in a basic debugfs top directory /sys/kernel/debug/qcom_camss for
the various blocks to hang register debug interfaces out of.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add in three additional stats registers which provide detail on packet
RX stats.

A subsequent patch will bring these stats out via debugfs.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Capture the hardware VFE version when we read it.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Print the CSIPHY index to keep the hw_version printout similar to the
VFE printout.

Process node geometery effectively disbarrs the PHY version being
different on different interfaces for the same SoC however, we should
align the output text between VFE and CSIPHY.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

The stream of VFE hardware identifiers has no index and thus little
meaning when viewing the printed output.

Add the index to provide context.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Switch off IO_STRICT_DEVMEM to allow debugcc to work.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Switch on the regulator option for the pm8008.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Switch on the pm8008 driver required for the camera sensors on x13s.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Switch on CAMSS for the x13s.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Switch on the OV5675 main RGB sensor for x13s.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

The ov5675 is at i2c address 0x20 located on pins
cci_i2c_sda5/cci_i2c_scl5 denoted as cci2_i2c1. MCLK3 is used to clock
the chip with vreg_l7q, vreg_l6q and vreg_l2q providing dovdd, avdd and
dvdd respectively.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

The RGB camera sensor uses MCLK3/gpio17 as clock with SC_RGB_XSHUT_N/gpio15
as reset.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

The IR camera sensor uses MCLK4/gpio6 as clock with SC_IR_XSHUT_N/gpio7
as reset.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Assign schematic vreg names to pm8008 LDOs.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add CAMSS block defintion for sc8280xp.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

As is pretty standard for Titan camera interfaces, sc8280xp has two
Camera Control Interface (CCI) blocks which pinout to two I2C master
controllers for each CCI.

The CCI I2C pins are not muxed so we define them in the dtsi.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

vfe-170 and vfe-175 can be supported in the same file with some minimal
indirection to differentiate between the silicon versions.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add a PHY configuration sequence for the sc8280xp which uses a Qualcomm
Gen 2 version 1.1 CSI-2 PHY.

The PHY can be configured as two phase or three phase in C-PHY or D-PHY
mode. This configuration supports two-phase D-PHY mode.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

fill this in

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This commit describes the hardware layout for the sc8280xp for the
following hardware blocks:

- 4 x VFE, 4 RDI per VFE
- 4 x VFE Lite, 4 RDI per VFE
- 4 x CSID
- 4 x CSID Lite
- 4 x CSI PHY

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Adds a CAMSS SoC identifer for the SC8280XP.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add sc8280xp using the standard new CCI V2 data with the correct i2c
address shift.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

In several of our dts files we specify the incorrect address for the
camera sensor as a result of shitfing left by four bits, instead of by
three bits.

We unfortunately have a number of dts files that specify the off-by-one
bit so we cannot simply fix in this driver.

For example: the sdm845-db845c-navigation-mezzanine.dts specifies the
ov8856 address as 0x10 however the schematic shows the address is in
fact 0x20.

Add a new struture with the correct bit-shift. We can add in new SoCs
against this corrected shift and similarly transition upstream dts to
new compatibles to correct their addressing whilst maintaining legacy
broken addressing support.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

On several versions of the CCI we currently shift one bit more than we
should:
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Probe deferral is a normal thing, there's no need to bring out an error
message for it.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>