Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

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Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
  "series": {
    "revision": 1,
    "change-id": "20240521-x1e80100-dts-external-dp-22dbee4097e4",
    "prefixes": []
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Neil Armstrong authored 9 months ago and Abel Vesa committed 8 months ago

If the thermal core tries to update the temperature from an
uninitialized power supply, it will swawn the following warning:
thermal thermal_zoneXX: failed to read out thermal zone (-19)

But reading from an uninitialized power supply should not be
considered as a fatal error, but the thermal core expects
the -EAGAIN error to be returned in this particular case.

So convert -ENODEV as -EAGAIN to express the fact that reading
temperature from an uninitialized power supply shouldn't be
a fatal error, but should indicate to the thermal zone it should
retry later.

It notably removes such messages on Qualcomm platforms using the
qcom_battmgr driver spawning warnings until the aDSP firmware
gets up and the battery manager reports valid data.

Link: https://lore.kernel.org/all/2ed4c630-204a-4f80-a37f-f2ca838eb455@linaro.org/


Fixes: 5bc28b93 ("power_supply: power_supply_read_temp only if use_cnt > 0")
Fixes: 3be330bf ("power_supply: Register battery as a thermal zone")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

This config is mostly based on Johan's defconfig from his github tree.

Not-Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

UCSI isn't working yet.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

So the PCIe 6 can be configured in 4-lane mode or 2-lane mode. For
4-lane mode, it fetches the lanes provided by PCIe 6b. For 2-lane mode,
PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. Configure
it in 4-lane mode and then each board can configure it depending on the
design. Both the QCP and CRD boards, currently upstream, use the 6a for
NVMe in 4-lane mode. Also, mark the controller as 4-lane as well.

Fixes: 5eb83fc1 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

# Describe the purpose of this series. The information you put here
# will be used by the project maintainer to make a decision whether
# your patches should be reviewed, and in what priority order. Please be
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Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
  "series": {
    "revision": 1,
    "change-id": "20240725-x1e80100-dts-pcie6-switch-4lanes-3604a6f06ac7",
    "prefixes": []
  }
}

The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or
2-lane mode. Add the configuration and compatible for the 4-lane mode.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or
2-lane mode. Document the 4-lane mode as a separate compatible.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

On both QCP and CRD board currently supported upstream, the NVMe sits
on the PCIe 6. Until now that has been configured in dual lane mode
only. The schematics reveal that the NVMe is actually using 4 lanes.
So add support for the 4-lane mode and document the compatible for it.

To: Vinod Koul <vkoul@kernel.org>
To: Kishon Vijay Abraham I <kishon@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: Johan Hovold <johan@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-phy@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

---
Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/20240531-x1e80100-phy-add-gen4x4-v1-0-5c841dae7850@linaro.org



--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
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    "revision": 2,
    "change-id": "20240531-x1e80100-phy-add-gen4x4-fa830a5505b6",
    "prefixes": [],
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        "20240531-x1e80100-phy-add-gen4x4-v1-0-5c841dae7850@linaro.org"
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Qiang Yu authored 8 months ago and Abel Vesa committed 8 months ago

Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

# Describe the purpose of this series. The information you put here
# will be used by the project maintainer to make a decision whether
# your patches should be reviewed, and in what priority order. Please be
# very detailed and link to any relevant discussions or sites that the
# maintainer can review to better understand your proposed changes. If you
# only have a single patch in your series, the contents of the cover
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# Lines starting with # will be removed from the cover letter. You can
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# these trailers will be added to the addresses specified/generated
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Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
  "series": {
    "revision": 1,
    "change-id": "20240725-phy-qcom-qmp-pcie-write-all-tbls-second-port-8efeced876bf",
    "prefixes": []
  }
}

Update to the latest configuration based on internal Qualcomm
documentation.

Fixes: 606060ce ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

# Describe the purpose of this series. The information you put here
# will be used by the project maintainer to make a decision whether
# your patches should be reviewed, and in what priority order. Please be
# very detailed and link to any relevant discussions or sites that the
# maintainer can review to better understand your proposed changes. If you
# only have a single patch in your series, the contents of the cover
# letter will be appended to the "under-the-cut" portion of the patch.

# Lines starting with # will be removed from the cover letter. You can
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# markdown headers in your cover letter, start the line with ">#".

# You can add trailers to the cover letter. Any email addresses found in
# these trailers will be added to the addresses specified/generated
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# modified.

To: Vinod Koul <vkoul@kernel.org>
To: Kishon Vijay Abraham I <kishon@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-phy@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: Johan Hovold <johan@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
  "series": {
    "revision": 1,
    "change-id": "20240725-x1e80100-phy-qmp-pcie-fix-config-a9bdc75fd9fe",
    "prefixes": []
  }
}

Confirmed by Qualcomm that the L0s should be disabled on this platform
as well.

Fixes: 6d0c3932 ("PCI: qcom: Add X1E80100 PCIe support")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Krzysztof Wilczyński <kw@linux.com>
To: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: Krzysztof Wilczyński <kwilczynski@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
  "series": {
    "revision": 1,
    "change-id": "20240725-x1e80100-pcie-disable-l0s-548a2f316eec",
    "prefixes": []
  }
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Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

The mapping of the PDC interrupts need to be double checked.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Advertise the same chipid as A740 to userspace for now, until
the whole chipid/revn gets sorted out.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>