- Sep 04, 2024
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Abel Vesa authoredSigned-off-by:Abel Vesa <abel.vesa@linaro.org>
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- Sep 03, 2024
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Abel Vesa authored
The Lenovo Yoga Slim 7x laptop has 3 USB Type-C ports, and just like the CRD, all of them supporting external DP altmode. Between each QMP combo PHY and the corresponding Type-C port, sits one Parade PS8830 retimer which handles both orientation and SBU muxing. Add nodes for each retimer, fix the graphs between connectors and the PHYs accordingly, add the voltage regulators needed by each retimer and then enable all 3 remaining DPUs. Signed-off-by: -
Abel Vesa authored
The orientation-switch is already set in the x1e80100 SoC dtsi. Signed-off-by:
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- Sep 02, 2024
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Abel Vesa authored
This config is mostly based on Johan's defconfig from his github tree. Not-Signed-off-by: -
Abel Vesa authored
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Abel Vesa authored
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Abel Vesa authored
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- Aug 30, 2024
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Abel Vesa authored
The Parade PS8830 is a Type-C muti-protocol retimer controlled over I2C. It provides both altmode and orientation handling. Add a driver with support for the following modes: - DP 4lanes - USB3 - DP 2lanes + USB3 Tested-by: Konrad Dybcio <quic_kdybcio@quicinc.com> # x1e80100-romulus Signed-off-by: -
Abel Vesa authored
Document bindings for the Parade PS8830 Type-C retimer. This retimer is currently found on all boards featuring Qualcomm Snapdragon X Elite SoCs and it is needed to provide altmode muxing between DP and USB. Tested-by: Konrad Dybcio <quic_kdybcio@quicinc.com> # x1e80100-romulus Signed-off-by: -
Abel Vesa authored
Fixes: ee3f0739 ("clk: qcom: Add dispcc clock driver for x1e80100") Signed-off-by:
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Abel Vesa authored
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Abel Vesa authored
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Abel Vesa authored
Add node uart14 for x1e80100. Co-developed-by:
Zijun Hu <quic_zijuhu@quicinc.com> Signed-off-by:
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As part of bus config before the bank switch happens, setup soundwire clk switching signal to indicate clk switch in frequency synchronously to codec digital core. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Check for SPF readiness in prm driver probe to avoid race conditions during ADSP pil loading. This patch is to avoid, sending requests to ADSP before it's PD's is up and ready. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Tested-by:
Ratna Deepthi Kudaravalli <rkudarav@qti.qualcomm.com> (cherry picked from commit b8d605823adfcb71fe3b3fa110dcf2fc2f53cb21) Signed-off-by:
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DSP expects the buffers to be aligned to 64bytes, so fix the current sizes where there is a possiblity of getting an unaligned buffers. Signed-off-by:
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For some reason on wsa883x we see Port Collision during bank swith, adding a delay seems provide a good workaround for this. Needs more investigation. Signed-off-by:
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Registering controller even before pm runtime is enabled will result in pm runtime underflow warnings. Fix this by properly moving the runtime pm enable before registering controller. Fixes: 74e79da9 ("soundwire: qcom: add runtime pm support") Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> (cherry picked from commit 7578d5a6e7e7f0e2457f330c5c10c5c0b09c900d) Signed-off-by:
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If the thermal core tries to update the temperature from an uninitialized power supply, it will swawn the following warning: thermal thermal_zoneXX: failed to read out thermal zone (-19) But reading from an uninitialized power supply should not be considered as a fatal error, but the thermal core expects the -EAGAIN error to be returned in this particular case. So convert -ENODEV as -EAGAIN to express the fact that reading temperature from an uninitialized power supply shouldn't be a fatal error, but should indicate to the thermal zone it should retry later. It notably removes such messages on Qualcomm platforms using the qcom_battmgr driver spawning warnings until the aDSP firmware gets up and the battery manager reports valid data. Link: https://lore.kernel.org/all/2ed4c630-204a-4f80-a37f-f2ca838eb455@linaro.org/ Fixes: 5bc28b93 ("power_supply: power_supply_read_temp only if use_cnt > 0") Fixes: 3be330bf ("power_supply: Register battery as a thermal zone") Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org>
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Abel Vesa authored
All three USB SS combo QMP PHYs need to power off, deinit, then init and power on again on every plug in event. This is done by forwarding the orientation from the retimer/mux to the PHY. All is needed is the orientation-switch property in each such PHY devicetree node. So add them. Fixes: 4af46b7b ("arm64: dts: qcom: x1e80100: Add USB nodes") Reviewed-by:
Konrad Dybcio <konradybcio@kernel.org> Signed-off-by:
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Abel Vesa authored
The actual PHY used by MDSS DP2 is the USB SS2 QMP one. So switch to it instead. This is needed to get external DP support on boards like CRD where the 3rd Type-C USB port (right-hand side) is connected to DP2. Fixes: 1940c25e ("arm64: dts: qcom: x1e80100: Add display nodes") Reviewed-by:
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Add support for the aforementioned laptop. That includes: - input methods, incl. lid switch (keyboard needs the pdc wakeup-parent removal hack..) - NVMe, WiFi - USB-C ports - GPU, display - DSPs Notably, the USB-A ports on the side are depenedent on the USB multiport controller making it upstream. At least one of the eDP panels used (non-touchscreen) identifies as BOE 0x0b66. See below for the hardware description from the OEM. Link: https://www.lenovo.com/us/en/p/laptops/thinkpad/thinkpadt/lenovo-thinkpad-t14s-gen-6-(14-inch-snapdragon)/len101t0099 Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org>
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Document the X1E78100-based ThinkPad. X1E78100 is a binned version of X1E80100, hence use the latter's compatible string as fallback. Signed-off-by:
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New GPUs still use the lower 2 bytes of the chip id (in whatever form it comes) to signify silicon revision. Drop the warning that makes it sound as if that was unintended. Fixes: 90b593ce ("drm/msm/adreno: Switch to chip-id for identifying GPU") Signed-off-by:
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Abel Vesa authored
Add support for the SHP 1505 panel. Signed-off-by: -
Abel Vesa authored
Enable the CPUCP mailbox controller driver as built-in. Needed by the new Qualcomm X1E80100 platform. Signed-off-by: -
Add a custom trimmed configuration that can be used to test SC8280XP and X1E80100 support including the Lenovo ThinkPad X13s, sc8280xp-crd, sa8295p-adp and x1e80100-crd. Make sure the initramfs includes any modules required to boot, for example: nvme phy_qcom_qmp_pcie pcie_qcom for the X13s, nvme tcsrcc_x1e80100 phy_qcom_qmp_pcie pcie_qcom for the x1e80100-crd, and phy_qcom_qmp_ufs ufs_qcom for the sc8280xp-crd with rootfs on UFS. For keyboard input and (more than 30 seconds of) display in initramfs, make sure to also include: i2c_hid_of i2c_qcom_geni for keyboard, and leds_qcom_lpg pwm_bl qrtr pmic_glink_altmode gpio_sbu_mux phy_qcom_qmp_combo gpucc_sc8280xp dispcc_sc8280xp phy_qcom_edp panel_edp msm for the display. For more details see: https://github.com/jhovold/linux/wiki/X13s Not-signed-off-by:
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Abel Vesa authored
So the PCIe 6 can be configured in 4-lane mode or 2-lane mode. For 4-lane mode, it fetches the lanes provided by PCIe 6b. For 2-lane mode, PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. Configure it in 4-lane mode and then each board can configure it depending on the design. Both the QCP and CRD boards, currently upstream, use the 6a for NVMe in 4-lane mode. Also, mark the controller as 4-lane as well. Fixes: 5eb83fc1 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Signed-off-by:
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The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0). Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed. Signed-off-by: -
The Gen4 stabilisation series currently relies on hardcoding the maximum link speed to have any effect. Signed-off-by: -
Commit 756485bf ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema") incorrectly removed 'vddpe-3v3-supply' from the bindings, which results in DT checker warnings like: arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dtb: pcie@600000: Unevaluated properties are not allowed ('vddpe-3v3-supply' was unexpected) from schema $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# Note that this property has been part of the Qualcomm PCIe bindings since 2018 and would need to be deprecated rather than simply removed if there is a desire to replace it with 'vpcie3v3' which is used for some non-Qualcomm controllers. Fixes: 756485bf ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema") Signed-off-by:
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The 32-bit BAR spaces are reaching outside their assigned register regions. Shrink them to match their actual sizes. While at it, unify the style. Fixes: 5eb83fc1 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Signed-off-by:
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Update the numbers based on the information found in the DSDT. Fixes: af16b005 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by:
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Abel Vesa authored
Add missing Broadcast_AND region to the LLCC block for x1e80100, as the LLCC version on this platform is 4.1 and it provides the region. This also fixes the following error caused by the missing region: [ 3.797768] qcom-llcc 25000000.system-cache-controller: error -EINVAL: invalid resource (null) Fixes: af16b005 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by:
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Abel Vesa authored
Confirmed by Qualcomm that the L0s should be disabled on this platform as well. So use the sc8280xp config instead. Fixes: 6d0c3932 ("PCI: qcom: Add X1E80100 PCIe support") Signed-off-by:
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Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. Signed-off-by:
Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20240612124056.39230-6-quic_sibis@quicinc.com Signed-off-by:
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Add the cpucp mailbox and sram nodes required by SCMI perf protocol on X1E80100 SoCs. Signed-off-by:
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Resize the GICR register region as it currently seeps into the CPU Control Processor mailbox RX region. Fixes: af16b005 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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